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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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SC2200 датащи(PDF) 204 Page - National Semiconductor (TI) |
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SC2200 датащи(HTML) 204 Page - National Semiconductor (TI) |
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204 / 433 page  www.national.com 204 Revision 3.0 Core Logic Module (Continued) 0 X-Bus Warm Start. Writing and reading this bit each have different meanings. When reading this bit, it indicates whether or not a warm start occurred since power-up: 0: A warm start occurred. 1: No warm start has occurred. When writing this bit, it can be used to trigger a system-wide reset: 0: No effect. 1: Execute system-wide reset (used only for clock configuration at power-up). Index 45h Reserved Reset Value: 00h Index 46h PCI Functions Enable Register (R/W) Reset Value: FEh 7:6 Reserved. Resets to 11. 5 F5 (PCI Function 5). When asserted (set to 1), enables the register space designated as F5. This bit must always be set to 1. (Default) 4 F4 (PCI Function 4). When asserted (set to 1), enables the register space designated as F4. This bit must always be set to 1. (Default) 3 F3 (PCI Function 3). When asserted (set to 1), enables the register space designated as F3. This bit must always be set to 1. (Default) 2 F2 (PCI Function 2). When asserted (set to 1), enables the register space designated as F2. This bit must always be set to 1. (Default) 1 F1 (PCI Function 1). When asserted (set to 1), enables the register space designated as F1. This bit must always be set to 1. (Default) 0 Reserved. Must be set to 0. Index 47h Miscellaneous Enable Register (R/W) Reset Value: 00h 7:3 Reserved. Must be set to 0. 2 F0BAR1 (PCI Function 0, Base Address Register 1). F0BAR1, pointer to I/O mapped LPC configuration registers. 0: Disable. 1: Enable. 1 F0BAR0 (PCI Function 0, Base Address Register 0). F0BAR0, pointer to I/O mapped GPIO configuration registers. 0: Disable. 1: Enable. 0 Reserved. Must be set to 0. Index 48h-4Bh Reserved Reset Value: 00h Index 4Ch-4Fh Top of System Memory (R/W) Reset Value: FFFFFFFFh 31:0 Top of System Memory. Highest address in system used to determine active decode for external PCI mastered memory cycles. If an external PCI master requests a memory address below the value programmed in this register, the cycle is transferred from the external PCI bus interface to the Fast-PCI interface for servicing by the GX1 module. Note: The four least significant bits must be set to 1100. Index 50h PIT Control/ISA CLK Divider (R/W) Reset Value: 7Bh 7 PIT Software Reset. 0: Disable. 1: Enable. 6 PIT Counter 1. 0: Forces Counter 1 output (OUT1) to zero. 1: Allows Counter 1 output (OUT1) to pass to the Port 061h[4]. 5 PIT Counter 1 Enable. 0: Sets GATE1 input low. 1: Sets GATE1 input high. Table 5-29. F0: PCI Header and Bridge Configuration Registers for GPIO and LPC Support (Continued) Bit Description |
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