ADP1055ACPZ-R7 datasheet(121/140 Pages) AD

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Data Sheet

ADP1055

Rev. A | Page 121 of 140

Table 213. Register 0xFE65—VOUT_DROOP_SETTING

Bits

Bit Name

R/W

Description

Snubber selection

R/W

0 = falling edge of SRx is used to activate the snubber.

1 = falling edge of OUTC or OUTD is used to activate the snubber.

[6:3]

Reserved

Reserved.

Disable VOUT_

TRANSITION_RATE

R/W

1 = disable. The voltage reference immediately jumps to the value set by VOUT_COMMAND.

0 = enable. The output voltage changes from one value to another as programmed by the

VOUT_TRANSITION_RATE command.

[1:0]

VOUT_DROOP

sampling rate

R/W

For the purposes of VOUT_DROOP, IOUT is sampled at the following intervals:

00 = 7 bits = 82 μs.

01 = 8 bits = 164 μs.

10 = 9 bits = 327 μs.

11 = 10 bits = 655 μs.

Table 214. Register 0xFE66—NC_BURST_MODE (Requires Use of the GO Bit in Register 0xFE00)

Bits

Bit Name

R/W

Description

[7:6]

ADC threshold

R/W

Burst occurs if the ADC error exceeds the specified threshold.

00 = error threshold > |±1%| of 1 V (that is, 10 mV)

01 = error threshold > |±2%| of 1 V (that is, 20 mV)

10 = error threshold > |±3%| of 1 V (that is, 30 mV)

11 = error threshold > |±4%| of 1 V (that is, 40 mV)

[5:3]

Number of burst

cycles

R/W

Set to 0 for no burst

Enable burst in

LLM/DEM only

R/W

1 = burst in light load mode and diode emulation mode only (not in CCM)

0 = burst in any mode

[1:0]

Burst magnitude

R/W

Magnitude of burst in percentage of duty cycle that is added to the present duty cycle

00 = 6.25%

01 = 12.5%

10 = 25%

11 = 50%

Table 215. Register 0xFE67—HF_ADC_CONFIG

Bits

Bit Name

R/W

Description

[7:4]

HF ADC samples

R/W

These bits specify the number of samples taken by the flash ADC for loop regulation. The number

of samples ranges from 1 (Bits[7:4] = 0000) to 16 (Bits[7:4] = 1111). Following are suggested values

depending on the frequency range and whether double update rate is enabled.

Frequency Range (kHz)

Double Update Rate Enabled

Double Update Rate Disabled

fSW ≤ 250

1111 (16 samples)

250 < fSW ≤ 300

0111 (8 samples)

1111 (16 samples)

300 < fSW ≤ 724.638

0011 (4 samples)

1111 (16 samples)

724.638 < fSW ≤ 1000

0001 (2 samples)

0111 (8 samples)

[3:0]

Reserved

R/W

Set these bits to 000 for proper operation.

Table 216. Register 0xFE80—VS_TRIM

Bits

Bit Name

R/W

Description

Gain polarity

R/W

1 = negative gain is introduced.

0 = positive gain is introduced.

[6:0]

Gain trim

R/W

These bits set the amount of gain trim that is applied to the VS ADC reading. This register trims

the voltage at the VS± pins for external resistor tolerances. The VS trim must be performed before

the load OVP and load UVP trims are performed. The total range for these bits is ±6.25%. The

LSB = (6.25%)/128.

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