82375EB datasheet(103/131 Pages) INTEL

103 / 131 page

82375EBSB

290477 – 68

Figure 25 EISA Memory and IO ReadWrite Cycle (One Extended and Two Standard Cycles)

712 EISA BACK-OFF CYCLE

For mismatched cycles to an EISAISA slave the PCEB as a master backs off the EISA Bus by floating the

START

BE 30

and SD 310 signals one and half BCLKs after START

has been asserted The ESC

controls the EISA Bus for the duration of the cycle This allows the ESC to perform data translation if

necessary At the end of the cycle the ESC transfers control back to the PCEB by asserting EX16

and

EX32

on the falling edge of BCLK before the rising edge of BCLK that the last CMD

is negated Refer to

the ESC data sheet for further details on master back-off and the cycle transfer control operations

Figure 26 shows an example of a back-off sequence during a 32-bit EISA master to 16-bit EISA slave Dword

read and write operation The thick lines indicate the change of control between the master and the ESC

PCEB Reading From a 16-bit EISA Slave

As a 32-bit EISA master the PCEB begins by placing the address on LA 312 and driving MIO

The 16-bit

EISA slave decodes the address and asserts EX16

The PCEB asserts START

and BE 30

The ESC samples EX32

and EX16

on the rising edge of BCLK following the assertion of START

and

asserts CMD

At the same time the PCEB negates START

and samples EX32

When EX32

is sampled

negated the PCEB floats START

and BE 30

Note that the PCEB continues to drive a valid address on

LA 310

103

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