82375EB datasheet(41/131 Pages) INTEL

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82375EBSB

WEWrite Enable

When the WE bit (bit 7 5 3 1) is set to a 1 the PCEB generates MEMCS

for PCI

master DMA or EISA master memory write accesses to the corresponding segment in main memory When

this bit is set to a 0 the PCEB does not generate MEMCS

for PCI master DMA or EISA master memory

write accesses to the corresponding segment When the RE and WE bits are both 0 (or bit 4 in the MEMCS

Control Register is set to a 0-disabled) the PCI master DMA or EISA master can not access the correspond-

ing segment in main memory

Bit

Description

0DC000 – 0DFFFFh Add-on BIOS WE

1eEnable 0eDisable

0DC000 – 0DFFFFh Add-on BIOS RE

1eEnable 0eDisable

0D8000 – 0DBFFFh Add-on BIOS WE

1eEnable 0eDisable

0D8000 – 0DBFFFh Add-on BIOS RE

1eEnable 0eDisable

0D4000 – 0D7FFFh Add-on BIOS WE

1eEnable 0eDisable

0D4000 – 0D7FFFh Add-on BIOS RE

1eEnable 0eDisable

0D0000 – 0D3FFFh Add-on BIOS WE

1eEnable 0eDisable

0D0000 – 0D3FFFh Add-on BIOS RE

1eEnable 0eDisable

3119 MAR3MEMCS

ATTRIBUTE REGISTER

Address Offset

56h

Default Value

00h

Attribute

ReadWrite

Size

8 bits

RERead Enable

When the RE bit (bit 6 4 2 0) is set to a 1 the PCEB generates MEMCS

for PCI master

DMA EISA master memory read accesses to the corresponding segment in main memory When this bit is set

to a 0 the PCEB does not generate MEMCS

for PCI master DMA or EISA master memory read accesses to

the corresponding segment When the RE and WE bits are both 0 (or bit 4 in the MEMCS

Control Register is

set to a 0-disabled) the PCI master can not access the corresponding segment in main memory

WEWrite Enable

When the WE bit (bit 7 5 3 1) is set to a 1 the PCEB generates MEMCS

for PCI

master DMA EISA master memory write accesses to the corresponding segment in main memory When this

bit is set to a 0 the PCEB does not generate MEMCS

for PCI master DMA or EISA master memory write

accesses to the corresponding segment When the RE and WE bits are both 0 (or bit 4 in the MEMCS

Control Register is set to a 0-disabled) the PCI master can not access the corresponding segment in main

memory

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