82375EB datasheet(63/131 Pages) INTEL

63 / 131 page

82375EBSB

NOTE

1 All signals are sampled on the rising edge of the PCI clock Each signal has a setup and hold

window with respect to the rising clock edge in which transitions are not allowed Outside of this

range signal values or transitions have no significance

2 The terms initiator and master are synonymous Likewise the terms target and slave are synony-

mous

3 Readers should be familiar with the PCI Bus specification

51 PCI Bus Transactions

This section presents the PCI Bus transactions supported by the PCEB

511 PCI COMMAND SET

PCI Bus commands indicate to the target the type of transaction requested by the master These commands

are encoded on the CBE 30

lines during the address phase of a transfer Table 5 summarizes the PCEB’s

support of the PCI Bus commands

Table 5 PCEB-Supported PCI Bus Commands

CBE 30

Command Type

Supported As Target

Supported As Initiator

0000

Interrupt Acknowledge

Yes

0001

Special Cycle

0010

IO Read

Yes

0011

IO Write

Yes

0100

Reserved

NA(3)

0101

Reserved

NA(3)

0110

Memory Read

Yes

0111

Memory Write

Yes

1000

Reserved

NA(3)

1001

Reserved

NA(3)

1010

Configuration Read

Yes

1011

Configuration Write

Yes

1100

Memory Read Multiple

No(2)

1101

Reserved

NA(3)

1110

Memory Read Line

No(2)

1111

Memory Write and Invalidate

No(1)

NOTES

1 As a target the PCEB treats this command as a memory write command

2 As a target the PCEB treats this command as a a memory read command

3 The PCEB considers a reserved command invalid and as a target completely ignores the transaction All internal ad-

dress decoding is ignored and the PCEB never asserts DEVSEL

As a PCI master the PCEB never generates a bus

cycle with a reserved command type

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