82375EB datasheet(68/131 Pages) INTEL

68 / 131 page

82375EBSB

5128 Memory Read Multiple

Target support

The PCEB aliases this command to a normal memory read cycle See the Memory Read command descrip-

tion

Initiator support

Memory read multiple cycles are never generated by the PCEB

5129 Memory Read Line

Target support

The PCEB aliases this command to a normal memory read See the Memory Read command description

Initiator support

Memory read line cycles are never generated by the PCEB

51210 Memory Write And Invalidate

Target support

Response

The PCEB treats this command like a memory write See the Memory Write command description

Initiator support

Cycle Generation Conditions

The PCEB does not generate this command cycle

513 PCI TRANSFER BASICS

The basic bus transfer mechanism on the PCI Bus is a burst A burst is comprised of an address phase and

one or more data phases The PCI protocol specifies the following types of burst ordering (signaled via A 10

during the address phase)

A 10

Burst Order

0 0

Linear Incrementing

0 1

Cache line toggle mode

1 X

Reserved

The PCEB only supports linear incrementing burst ordering as an initiator Data transfers for ordering other

than linear incrementing are disconnected by the PCEB (burst split into multiple single data transfers)

The fundamentals of all PCI data transfers are controlled with the following three signals

FRAME

is driven by the PCI master to indicate the beginning and end of a transaction

IRDY

is driven by the PCI master allowing it to force wait states

TRDY

is driven by the PCI target allowing it to force wait states

The PCI Bus is idle when both FRAME

and IRDY

are negated The first clock edge that FRAME

sampled asserted is the address phase and the address and bus command code are transferred on that clock

edge The next clock edge begins the first of one or more data phases During the data phases data is

transferred between master and slave on each clock edge that both IRDY

and TRDY

are sampled assert-

ed Wait states may be inserted by either the master (by negating IRDY ) or the target (by negating TRDY )

When a PCI master has one more data transfer to complete the cycle (which could be immediately after the

address phase) it negates FRAME

IRDY

must be asserted at this time indicating that the master is ready

for the final data transfer After the target indicates the final data transfer (TRDY

asserted) the master

negates IRDY

causing the target’s PCI interface to return to the idle state (FRAME

and IRDY

negated)

on the next clock edge

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