82375EB datasheet(71/131 Pages) INTEL

71 / 131 page

82375EBSB

514 BASIC READ

As a PCI master

the PCEB performs memory and IO read transfers Figure 7 shows a PCEB zero wait state

burst read from PCI memory (PCEB is a master) If buffering of memory accesses is enabled read transfers

use prefetching When reading data from PCI memory the PCEB requests a minimum of 16 bytes (one data

line of the Line Buffer) via a four data phase burst read cycle to fill one of its internal Line Buffers The PCEB

does not buffer PCI IO reads and only required data is transferred during these cycles Read Cycles to PCI

are generated on behalf of EISAISA masters and DMA devices

The PCEB asserts FRAME

on clock 1 and places the address on AD 312 CBE 30

contain a valid bus

command AD 10 contain the byte address for IO cycles burst order indication for memory cycles and are

00 for configuration cycles

The clock following the address phase is the beginning of the data phase During the data phase CBE 30

indicate which byte lanes are involved in the transaction If the byte lanes involved in the transaction are

different for data 1 and data 2 the PCEB drives new CBE 30 values on clock 4 CBE 30

remain active

until the end of the burst transfer

The first data phase of a read transaction requires a turn-around-cycle which is enforced by the target

preventing the assertion of TRDY

until at least clock 3 The PCEB stops driving the address at clock 2 The

target can not drive the AD bus until clock 3 This allows enough time for the PCEB to float its AD outputs The

target is required to drive the AD lines as soon as possible after clock 3 even though valid data may not be

ready and the target may want to stretch the initial data phase by delaying TRDY

This insures that the AD

lines are not left floating for long intervals The target must continue to drive these lines until the end of the

burst transaction

A single data phase is completed when the initiator of the cycle samples TRDY

asserted on the same clock

that IRDY

is asserted To add wait states the target must negate TRDY

for one or more clock cycles As a

master the PCEB does not add wait states In Figure 7 data is transferred on clocks 4 and 5 The PCEB

knows at clock 6 that the next data phase is the last and negates FRAME

As noted before the PCEB can

burst a maximum of four data cycles when reading from PCI memory

As a PCI target

the PCEB responds to both IO and memory read transfers Figure 8 shows the PCEB as a

target responding to a PCI master read cycle For multiple read transactions the PCEB always target termi-

nates after the first data read transaction by asserting STOP

and TRDY

These signals are asserted at the

end of the first data phase For single read transactions the PCEB completes the cycle in a normal fashion (by

asserting TRDY

without asserting STOP ) Figure 8 shows the fastest PCEB response to an access of an

internal configuration register During EISA Bus read accesses the PCEB always adds wait states by negating

TRDY

until the transfer on the EISA Bus is completed

When the PCEB as a target samples FRAME

active during a read cycle and positively decodes the cycle it

asserts DEVSEL

on the following clock (clock 3 in Figure 8) Note that if the PCEB subtractively or negative-

ly (82374SB only) decodes the cycle DEVSEL

is not asserted for two to three PCICLK’s after FRAME

sampled active (see Section 519 Device Selection) When the PCEB asserts DEVSEL

it also drives

AD 310 even though valid data is not available TRDY

is also driven from the same clock edge but it is not

asserted until the PCEB is ready to drive valid data TRDY

is asserted on the same clock edge that the PCEB

drives valid data on AD 310

If the PCEB presents valid read data during the first data phase and FRAME

remains active (multiple transaction indicated) the PCEB asserts TRDY

and STOP

to indicate target

termination of the transfer

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