82375EB datasheet(98/131 Pages) INTEL

98 / 131 page

82375EBSB

61 Line Buffers

The PCEB contains four Line Buffers that are each four Dwords wide (16 bytes) The Line Buffers are bi-direc-

tional and are used by the EISAISA master and DMA to assembledisassemble data The data in each Line

Buffer is aligned on 16 byte boundaries When data is placed in one of the Line Buffers the PCEB maintains

the corresponding 16-byte boundary address until the data in the line is transferred to its destination or

invalidated

The Line Buffers can be enableddisabled by writing to the PCICON Register In addition when the Line

Buffers are enabled via the PCICON Register buffering for accesses to the four programmable EISA-to-PCI

memory regions (Region 41 ) can be selectively disabled via the EPMRA Register

During buffer operations the four Line Buffers collectively are either in a write state or in a read state These

states are described in the following sections

611 WRITE STATE

If a Line Buffer contains valid write data it is in a

write state In the write state data from the EISAISA master

or DMA is posted in the Line Buffers Posting means that the write operation on the EISA Bus completes when

the data is latched in the buffer The EISA master does not have to wait for the write to complete to its

destination (memory on the PCI Bus) Posting permits the EISA Bus cycle to complete in a minimum time and

permits concurrent EISA and PCI Bus operations During posting data accumulates in the Line Buffer until it is

flushed (written to PCI memory) over the PCI Bus A Line Buffer is scheduled for flushing by the PCEB when

the line becomes full

a subsequent write is a line miss (not within the current line boundary address range)

the write is to an address of a lower Dword than the previous write Note that writes to lower addresses

within the same Dword do not cause a flush Note also that if two (or more) consecutive EISA Bus cycles

are writes to the same Dword (ie the same byte or word locations within the Dword or the same Dword for

Dword writes) the accessed buffer data is overwritten However if any of the flush conditions described in

this list occur between the writes the line is flushed before the next write and data is not overwritten

the last address location in the Line Buffer is accessed

a subsequent cycle is a read

the EISA Bus changes ownership

an interrupt acknowledge cycle is encountered

the ESC performs an EISA refresh cycle

the ESC’s IO APIC receives an interrupt request

When a line is scheduled for flushing the PCEB begins arbitration for the PCI Bus If more than one line is

scheduled to be flushed the Line Buffers are flushed in a ‘‘first scheduled first to be flushed’’ order If the line

to be flushed contains valid data in only one Dword the PCEB uses a single data transfer cycle on the PCI

Bus Otherwise flushing operations use burst transfers

During flushing write data within a Line Buffer is packetized into Dword quantities when possible for a burst

transfer over the 32-bit PCI Bus Packetizing occurs at two levels - Dwords within a line and byteswords within

a Dword When a Line Buffer is flushed all of the valid Dwords within the line are packetized into a single PCI

burst write cycle In addition all valid data bytes within a Dword boundary are packetized into a single data

phase of the burst cycle Packetizing reduces the PCI arbitration latency and increases the effective PCI Bus

bandwidth When multiple Line Buffers are schedule for flushing each Line Buffer is packetized separately

Packetizing across Line Buffer boundaries is not permitted

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