82375EB datasheet(45/131 Pages) INTEL

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82375EBSB

Bit

Description

Reserved

Region 4 Attribute (REG-4)

EISA accesses to this PCI memory region are buffered when this bit is 1

and non-buffered when this bit is 0 If the Line Buffers are disabled via the PCICON Register (bit 6)

buffering is disabled regardless of the value of this bit

Region 3 Attribute (REG-3)

EISA accesses to this PCI memory region are buffered when this bit is 1

and non-buffered when this bit is 0 If the Line Buffers are disabled via the PCICON Register (bit 6)

buffering is disabled regardless of the value of this bit

Region 2 Attribute (REG-2)

EISA accesses to this PCI memory region are buffered when this bit is 1

and non-buffered when this bit is 0 If the Line Buffers are disabled via the PCICON Register (bit 6)

buffering is disabled regardless of the value of this bit

Region 1 Attribute (REG-1)

EISA accesses to this PCI memory region are buffered when this bit is 1

and non-buffered when this bit is 0 If the Line Buffers are disabled via the PCICON Register (bit 6)

buffering is disabled regardless of the value of this bit

3123 MEMREGN 41

EISA-TO-PCI MEMORY REGION ADDRESS REGISTERS

Address Offset

60-63h (Memory Region 1)

64-67h (Memory Region 2)

68-6Bh (Memory Region 3)

6C-6Fh (Memory Region 4)

Default Value

0000FFFFh

Attribute

ReadWrite

Size

32 bits

These 32-bit registers provide four windows for EISA-to-PCI memory accesses Each window defines a posi-

tively decoded programmable address region for mapping EISA memory space to the corresponding PCI

memory space This base and limit address fields define the size and location of the region within the 4 GByte

PCI memory space The base and limit addresses can be aligned on any 64 KByte boundary and each region

can be sized in 64 KByte increments up to the theoretical maximum size of 4 GByte The default values of this

A region is selected based on the following formula Base Address s address s Limit Address

Bit

Description

3116

Memory Region Limit Address

For EISA-to-PCI accesses bits 3116 correspond to address

lines LA 3116 on the EISA Bus and AD 3116 on the PCI Bus This field determines the limit

address of the memory region within the 4 GByte PCI memory space

150

Memory Region Base Address

For EISA-to-PCI accesses bits 150 correspond to address lines

LA 3116 on the EISA Bus and AD 3116 on the PCI Bus This field determines the starting

address of the memory region within the 4 GByte PCI memory space

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