82375EB datasheet(74/131 Pages) INTEL

74 / 131 page

82375EBSB

290477 – A1

Figure 11 Configuration Cycle

517 INTERRUPT ACKNOWLEDGE CYCLE

The PCEB responds to an interrupt acknowledge cycle as decoded from the command during a valid address

cycle (FRAME

asserted) The AD bus itself is a ‘‘don’t care’’ to the PCEB during the address phase and

therefore status of the internal PCI address decoder is not used for forwarding the cycle to the EISA Bus

where the system interrupt controller resides

The PCEB converts the PCI interrupt acknowledge cycle into an EISA IO read access to the address 04h

with special semantics indicated to the ESC via the inter-chip signaling Before the PCI interrupt acknowledge

cycle can be converted into an EISA IO read cycle the EISA Bus must be owned If the EISA Bus is not

owned by the PCEB (EISAHLDA asserted) the PEREQ

INTA

signal is asserted with PEREQ

semantics

(PCI-to-EISA request) After the EISA Bus is acquired by the PCEB the interrupt acknowledge sequence can

proceed The PCEB starts an IO read cycle to address 04h and asserts PEREQ

INTA

with INTA

semantics The PEREQ

INTA

remains asserted for the duration of the EISA IO read cycle Therefore

only a single pulse is generated on the PEREQ

INTA

signal Conversion of the single PCI interrupt ac-

knowledge cycle into two interrupt acknowledge pulses (that is required for 8259 compatibility) occurs inside

the ESC where the 8259-based interrupt controller resides The ESC’s EISA decoder uses the PEREQ

INTA

signal (with INTA

semantics) to distinguish between normal IO reads to the register located at

address 04h (DMA1 Ch2 Base and Current Address) and the interrupt acknowledge sequence The ESC holds

the EISA Bus in wait states until the interrupt vector is returned to the PCEB (via SD 70 ) The PCEB passes

the vector to the PCI via AD 70 and then terminates the cycles both on EISA and PCI Note that for

compatibility reasons only the ESC (containing the DMA controller) can respond to the EISA IO read from

04h

Figure 12 shows the PCI portion of the interrupt acknowledge sequence The EISA portion of the sequence

matches normal EISA IO read timing except that the PEREQ

INTA

inter-chip signal is asserted during

the bus cycle with INTA

semantics and during the PCEBESC EISA Bus ownership exchange handshake

with PEREQ

semantics Note that the PCEB responses to a PCI interrupt acknowledge cycle can be dis-

abled by setting bit 5 in the PCI Control Register (PCICON) to 0

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