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82375EB датащи(PDF) 75 Page - Intel Corporation |
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82375EB датащи(HTML) 75 Page - Intel Corporation |
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75 / 131 page ![]() 82375EBSB 290477 – 54 Figure 12 PCI Interrupt Acknowledge Cycle 518 EXCLUSIVE ACCESS Refer to Figure 13 Figure 14 and Figure 15 for exclusive access timing relationships Target support PCI provides an exclusive access mechanism that allows non-exclusive accesses to proceed in the face of exclusive accesses This is referred to as a Resource Lock (Note that the exclusive access mechanism that locks the entire bus is Bus Lock) The PCEB as a resource can be locked by any PCI initiator In the context of locked cycles the PCEB and entire EISA subsystem are considered a single resource (EISA subsystem is indirectly locked during an exclusive access to the PCEB) A locked access to any address contained within the EISA subsystem locks the entire subsystem from the PCI side The PLOCK signal is propagated to the EISA LOCK signal Note that write posting (PCI-to-EISA) is disabled for PCI locked cycles propagated to the EISA subsystem The EISA Bus is not released to ESC until the locked sequence is complete A subsequent PCI initiator access to the EISA subsystem while it is locked results in a retry The PCEB becomes locked when it is the target of the access and PLOCK is sampled negated during the address phase The PCEB remains locked until FRAME and PLOCK are both sampled negated When in a locked state the PCEB only accepts requests when PLOCK is sampled negated during the address phase If PLOCK is asserted during the address phase the PCEB responds by asserting STOP with TRDY negated (RETRY) As an unlocked target the PCEB ignores PLOCK when deciding if it should respond to a PCI address decoder hit Also if PLOCK is sampled asserted during an address phase the PCEB does not go into a locked state As a locked target the PCEB responds to an initiator when it samples PLOCK negated during the address phase of the cycle in which the PCEB is the target of the access The locking master may negate PLOCK at the end of the last data phase When FRAME and PLOCK are both sampled negated the PCEB goes to the unlocked state Note that the PCEB does not release the EISA Bus when it is in the locked state 75 |
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