82375EB datasheet(95/131 Pages) INTEL

95 / 131 page

82375EBSB

7 When the EISA Bus is no longer owned by an EISA master or DMA the PCEB negates MEMREQ

and

FLSHREQ

and the PCI request signal (internal PCEBREQ

The negation of MEMREQ

and

FLSHREQ

indicates that direct access to the resource behind the bridge is no longer needed and that the

posted write buffers may be enabled Note that MEMACK

should be driven inactive as soon as possible

by the HostPCI Bridge and other bridges after MEMREQ

is negated The PCEB waits until it detects

MEMACK

negated before it can generate another MEMREQ

or FLSHREQ

The use of MEMREQ

FLSHREQ

and MEMACK

does not guarantee GAT mode functionality with ISA

masters that don’t acknowledge CHRDY These signals just guarantee the CHRDY inactive specification

5453 Interrupt Synchronization-Buffer Flushing

The ESC contains the system interrupt controller consisting of an 8259 compatible interrupt controller and an

IO APIC For the 8259 compatible interrupt controller the PCEBESC chip set is the default destination of the

PCI interrupt acknowledge cycles Interrupts in the system are commonly used as a synchronization mecha-

nism If interrupts are used by the EISA agents to notify the Host CPU that data is written to main memory then

posted data buffers must be flushed before the vector is returned during the interrupt acknowledge sequence

The PCEB handles this transparently to the rest of the system hardwaresoftware It retries the PCI interrupt

acknowledge cycles and flushes the PCEB Line Buffers if necessary

The Advanced Programmable Interrupt Controller (APIC) uses a private message passing bus to send interrupt

information to the companion APIC(s) residing at the host CPU(s) To support interrupts as a synchronization

mechanism system buffer coherency must be guaranteed before interrupts can be processed With ESC’s

interrupt controller operating in APIC mode the PCEB and ESC use the PCEBESC interchip signal AFLUSH

to maintain system buffer coherency

546 BUS PARKING

PCI Bus parking can be enableddisabled via the ARBCON Register Parking is only allowed for the device

that is connected to CPUREQ

(ie the HostPCI Bridge) REQ 30

and the internal PCEBREQ

are not

allowed to park on the PCI Bus When bus parking is enabled CPUGNT

is asserted when no other agent is

currently using or requesting the bus This achieves the minimum PCI arbitration latency possible

Arbitration Latency

Parked

0 PCICLKs for parked agent 2 PCICLKs for all other

Not Parked 1 PCICLK for all agents

Upon assertion of CPUGNT

due to bus parking enabled and the PCI Bus idle the CPU (ie parked agent)

must ensure AD 310

CBE 30

and (one PCICLK later) PAR are driven If bus parking is disabled then

the PCEB drives these signals when the bus is idle

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