82375EB datasheet(22/131 Pages) INTEL

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82375EBSB

Pin Name

Type

Description

SLBURST

SLAVE BURST

SLBURST

is an input when the PCEB is an EISA master and an

output when the PCEB is a slave

When the PCEB is a master the slave indicates that it supports burst cycles by

asserting SLBURST

to the PCEB The PCEB samples SLBURST

on the rising

edge of BCLK at the end of START

for EISA master cycles

When the PCEB is an EISA slave this signal is an output As a slave the PCEB

asserts this signal to the master indicating that the PCEB supports EISA burst cycles

During reset this signal is tri-stated

LOCK

When asserted LOCK

guarantees exclusive memory access This signal is

asserted by the PCEB when the PCI master is running locked cycles to EISA slaves

When asserted this signal locks the EISA subsystem

LOCK

can also be activated by a device on the EISA Bus This condition is

propagated to the PCI Bus via the PLOCK

signal During reset this signal is tri-

stated

BE 30

BYTE ENABLES

BE 30

identify the specific bytes that are valid during the

current EISA Bus cycles When the PCEB is an EISA master and the cycles are

directed to a matched slave (slave supports 32-bit transfers) the BE 30

are

outputs from the PCEB

When the cycles are directed to a mis-matched slave (slave does not support 32-bit

transfers - see note) the BE 30

are floated one and half BCLKs after START

asserted These signals become inputs (driven by the ESC) for the rest of the cycle

BE 30

are pipelined signals and must be latched by the addressed slave When

the PCEB is an EISAISADMA slave BE 30

are inputs to the PCEB

Upon PCIRST

these signals are tri-stated and placed in output mode

LA 3124

LATCHABLE ADDRESS

LA 3124

and LA 232 are the EISA address signals

When the PCEB is an EISA master these signals are outputs from the PCEB These

LA 232

addresses are pipelined and must be latched by the EISA slave LA 3124

and

LA 232 are valid on the falling edge of START

Note that the upper address bits

are inverted before being driven on LA 3124

The timing for LA 3124 and

LA 232 are the same

When the PCEB is an EISA slave these signals are inputs and are latched by the

PCEB

For IO cycles the PCEB as an EISA master floats LA 3124

to allow for ESC’s

address multiplexing (during IO cycle to configuration RAM) LA 232 are actively

driven by the PCEB For memory cycles the PCEB as an EISA master drives the LA

address lines During reset these signals are tri-stated

82375EB датащи(PDF) 22 Page - Intel Corporation

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