82375EB datasheet(64/131 Pages) INTEL

64 / 131 page

82375EBSB

512 PCI CYCLE DESCRIPTIONS

Each PCI Command is listed below with the following format of information

Command Type

PCEB target support

-Decode method

-Data path

-PCEB response

-Result of no response on EISA

PCEB initiator support

-Data path

-Conditions for generating command

-Result of no response on PCI

5121 Interrupt Acknowledge

Target support

Decode

Positive

Data Path

Flow through

Response

The interrupt acknowledge cycle is subject to retry If the PCEB is locked or if the interrupt acknowledge cycle

triggers buffer management activity or if the EISA Bus is occupied by an EISAISA master or the DMA the

interrupt acknowledge cycle is retried

The interrupt acknowledge command is a single byte read that is implicitly addressed to the interrupt controller

in the ESC component The address bits are logical ‘‘don’t cares’’ during the address phase and the byte

enables indicate to the PCEB that an 8-bit interrupt vector is to be returned on byte 0 After performing the

necessary buffer management operations and obtaining ownership of the EISA Bus the PCEB generates a

single pulse on the PEREQ

INTA

inter-chip signal and performs an IO read cycle (on the EISA Bus) to

the ESC internal registers residing at IO address 04h The ESC decode logic uses the PEREQ

INTA

signal to distinguish between standard accesses to IO address 04h (DMA controller) and special accesses

that result in a vector being read by the PCEB The PCEB holds the PCI Bus in wait states until the interrupt

vector is returned PEREQ

INTA

remains asserted until the end of the read cycle

Result of no response on EISA

The PCEB runs a standard length EISA IO read cycle and terminates normally The value of the data returned

as an interrupt vector is meaningless

Initiator support

None

NOTE

The PCEB only responds to PCI interrupt acknowledge cycles if this operation is enabled via bit 5 of

the PCICON Register)

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