82375EB datasheet(69/131 Pages) INTEL

69 / 131 page

82375EBSB

For IO cycles PCI addressing is on byte boundaries and all 32 AD lines are decoded to provide the byte

address For memory cycles AD 10 are used to define the type of burst ordering For configuration cycles

DEVSEL

is strictly a function of IDSEL

Configuration registers are selected as Dwords using AD 72 The

AD 10 must be 00 for the target to directly respond to the configuration cycle The byte enables determine

which byte lanes contain valid data

Each PCI agent is responsible for its own positive address decode Only one agent (the PCEB) on the PCI Bus

may use subtractive decoding The little endian addressing model is used

The byte enables are used to determine which bytes carry meaningful data These signals are permitted to

change between data phases The byte enables must be driven valid from the edge of the clock that starts

each data phase and must stay valid for the entire data phase Figure 7 the data phases begin on clocks 3

and 4 (Changing byte enables during a read burst transaction is generally not useful but is supported on the

bus) The master is permitted to change the byte enables on each new data phase although the read diagram

does not show this The timing for changing byte enables is the same for read and write transactions If byte

enables are important for the target on a read transaction the target must wait for the byte enables to be

driven on each data phase before completing the transfer

5131 Turn-Around-Cycle Definition

A turn-around-cycle is required on all signals that may be driven by more than one agent The turn-around-cy-

cle is required to avoid contention when one agent stops driving a signal and another agent begins and must

last at least one clock The symbol that represents a turn-around-cycle in the timing relationship figures is a

circular set of two lines each with an arrow that points to the other’s tail This turn-around-cycle occurs at

different times for different signals For example the turn-around-cycle for IRDY

TRDY

and DEVSEL

occurs during the address phase and for FRAME

CBE

and AD it occurs during the idle cycle

5132 Idle Cycle Definition

The cycle between clocks 7 and 8 in Figure 8 is called an idle cycle Idle cycles appear on the PCI Bus

between the end of one transaction and the beginning of the next An idle cycle occurs when both FRAME

and IRDY

are negated

82375EB датащи(PDF) 69 Page - Intel Corporation