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82375EB датащи(PDF) 18 Page - Intel Corporation |
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82375EB датащи(HTML) 18 Page - Intel Corporation |
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18 / 131 page ![]() 82375EBSB 22 PCI Arbiter Signals Pin Name Type Description CPUREQ in CPU REQUEST CPUREQ asserted indicates that the Host CPU requests use of the PCI Bus During PCIRST this signal must be sampled high by the PCEB When PCIRST is asserted (and CPUREQ is sampled high) the PCEB drives the AD CBE and PAR signals to keep them from floating REQ 30 in REQUEST A bus master asserts the corresponding request signal to request the PCI Bus CPUGNT out CPU GRANT The PCEB asserts CPUGNT to indicate that the CPU master (Host Bridge) has been granted the PCI Bus During PCI reset CPUGNT is tri-stated GNT 30 out GRANT The PCEB asserts one of the GNT 30 signals to indicate that the corresponding PCI master has been granted the PCI Bus During PCI reset these signals are tri-stated MEMREQ out MEMORY REQUEST If the PCEB is configured in Guaranteed Access Time (GAT) Mode MEMREQ is asserted when an EISA device or DMA requests the EISA Bus The PCEB asserts this signal (along with FLSHREQ ) to indicate that the PCEB requires ownership of main memory The PCEB asserts FLSHREQ concurrently with asserting MEMREQ This signal is synchronous to the PCI clock During reset this signal is driven high FLSHREQ MEMREQ Meaning 1 1 Idle 0 1 Flush buffers pointing towards PCI to avoid ISA deadlock 1 0 GAT enabled or disabled For buffer coherency in APIC systems the buffers pointing to main memory must be flushed and disabled for the duration of assertion 0 0 GAT mode Guarantee PCI Bus immediate access to main memory (this may or may not require the PCI-to-main memory buffers to be flushed first depending on the number of buffers) FLSHREQ out FLUSH REQUEST FLSHREQ is asserted by the PCEB to command all of the system’s posted write buffers pointing towards PCI to be flushed This is required before granting the EISA Bus to an EISA master or the DMA Note that for APIC related buffer flush requests this signal is negated This signal is synchronous to the PCI clock During reset this signal is driven high 18 |
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