82375EB datasheet(61/131 Pages) INTEL

61 / 131 page

82375EBSB

For EISA-to-PCI transactions there are 2 modes of operation of the PCEB’s Line Buffers

Buffered Read-prefetch write posting with data assembly

Non-buffered Bypass path used

Accesses within the main memory address range are normally performed in buffered mode If there are

programmable memory regions defined within the main memory hole or above the top of the main memory

MEMREGN 41

then the mode of access depends on configuration bits of the EPMRA Register Access

attribute bits associated with these regions override the default buffered mode for a particular address range in

the case of programmable regions overlapping with active main memory regions

Access to the 64 KByte area at the top of 16 MBytes (FF0000 – FFFFFFh) on the PCI if this region is within

main memory or within the main memory hole and enabled via the EADC2 Register are always forwarded in a

non-buffered mode unless overlapped with a programmable region that defines buffered access mode

422 PROGRAMMABLE EISA-TO-PCI MEMORY ADDRESS REGIONS

The PCEB supports four programmable memory regions for EISA-to-PCI transfers The PCEB positively de-

codes EISA memory accesses to these regions and forwards the cycle to the PCI Bus This feature permits

EISA master accesses to PCI devices that reside within these address ranges

Regions can be enabled or disabled After reset all regions are disabled Each region has an associated Base

and Limit Address fields MEMREGN 41 that determine the size and location of each region These registers

are programmed with the starting address of the region (Base) and ending address of the region (Limit) The

address range for a particular region is defined by the following equation

Base

Address s Address s Limit

Address

These regions can be defined anywhere in the 4 GByte address space at 64 KByte boundaries and with

64 KByte granularity In practical applications the regions will be mapped within the main memory hole or

above the top of the memory defined by the MEMCS

map

Access to the memory locations within a region can be performed in one of two modes

Non-Buffered Mode PCEB’s EISA-to-PCI Line Buffers can be disabled for all EISA-to-PCI memory read

write accesses through the PCICON Register or for selected accesses through EPMRA Register

Buffered Mode Line Buffers enabled Read-prefetch and write-assemblyposting allowed (without strong

ordering)

Since buffered mode provides maximum performance (and concurrency in non-GAT mode) it should be

selected unless the particular region is used for memory-mapped IO devices IO devices can not be ac-

cessed in read-prefetch or write-assemblyposted fashion because of potential side-effects (see Section 60

Data Buffering)

423 PROGRAMMABLE EISA-TO-PCI IO ADDRESS REGIONS

The PCEB provides four programmable IO address regions These regions are defined by Base and Limit

addresses fields contained in the associated IOREGN 41 Registers These regions can be defined anywhere

within the 64 KByte IO space on Dword boundaries (and with Dword granularity) See Section 41 PCEB

Configuration Registers

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