82375EB datasheet(65/131 Pages) INTEL

65 / 131 page

82375EBSB

5122 Special Cycle

Target support

None

Initiator support

None

5123 IO Read

Target support

Decode

Positive (PCEB and some ESC registers)

Subtractive

Data Path

Flow through

Response

The PCEB claims IO read cycles via positive or subtractive decoding and generates DEVSEL

The internal

PCEB registers (BIOS Timer) and the IDE and the 8259 registers are positively decoded Any unclaimed cycle

below 64 KByte is subtractively decoded and forwarded to the EISA Bus The IO read cycle is subject to retry

If the PCEB is locked if the cycle triggers buffer management activity or if the EISA Bus is occupied by an

EISAISA master or the DMA the IO read cycle is retried If the cycle gets retried due to an occupied EISA

Bus the EISA Bus is requested

Once an IO read cycle is accepted (not retried) by the PCEB the PCI Bus is held in wait states using TRDY

until the cycle is completed internally or on the EISA Bus

Burst IO reads to the EISA Bus or to the PCEB are not supported Therefore any burst IO read cycles

decoded by the PCEB are target terminated after the first data transaction using the disconnect semantics of

the STOP

signal (Disconnect A)

Result of no response on EISA The PCEB runs a standard length EISA IO cycle and terminates normally

Initiator support

The PCEB generates PCI Bus IO read cycles on behalf of an EISA master EISA cycles are forwarded to the

PCI Bus if the IO address is within one of four programmable IO address regions as defined in Section 40

Address Decoding

Result of no response on PCI Master abort due to DEVSEL

time-out PCEB returns data value FFFFFFFFh

5124 IO Write

Target support

Decode

Positive (PCEBESC registers)

Subtractive

Data Path

Flow through

Response

IO write cycles can be claimed by the PCEB via positive or subtractive decoding In either case the PCEB

generates DEVSEL

The internal PCEB registers (BIOS Timer) IDE registers and 8259 registers are positive-

ly decoded if enabled Any unclaimed cycle below 64 KByte is subtractively decoded and forwarded to the

EISA Bus The IO write cycle is subject to retry If the PCEB is locked if the cycle triggers buffer management

activity or if the EISA Bus is occupied by an EISAISA master or the DMA the IO write cycle is retried If the

cycle is retried due to an occupied EISA Bus the EISA Bus is requested

Once an IO write cycle is accepted (not retried) by the PCEB the PCI Bus is held in wait states using TRDY

until the cycle is completed within the PCEB or on the EISA Bus

Burst IO writes to the EISA Bus or to the PCEB are not supported Therefore any burst IO write cycles

decoded by the PCEB are target terminated after the first data transaction using the disconnect semantics of

the STOP

signal (Figure 5-12 Disconnect A)

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