82375EB datasheet(32/131 Pages) INTEL

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82375EBSB

316 MLTMASTER LATENCY TIMER REGISTER

Address Offset

0Dh

Default Value

00h

Attribute

ReadWrite

Size

8 bits

This 8-bit register contains the programmable value of the Master Latency Timer for use when the PCEB is a

master on the PCI Bus The granularity of the timer is 8 PCI clocks Thus bits 20 are not used and always

read as 0s

Bit

Description

Count Value

This 5-bit field contains the count value of the Master Latency Timer with a granularity

of 8 PCI clocks For example value 00101b provides a time-out period of 5x8e40 PCI clocks

Maximum count value is 11111b which corresponds to 248 PCI clocks

Reserved

317 PCICONPCI CONTROL REGISTER

Address Offset

40h

Default Value

20h

Attribute

ReadWrite

Size

8 bits

This 8-bit register enablesdisables the PCEB’s data buffers defines the subtractive decoding sample point

and enablesdisables response to the PCI interrupt acknowledge cycle

NOTE

The Line Buffers are typically enabled or disabled during system initialization These buffers should

not be dynamically enableddisabled during runtime Otherwise data coherency can be affected if a

buffer containing valid write data is disabled and then later re-enabled

Bit

Description

Reserved

EISA-To-PCI Line Buffer Enable (ELBE)

When ELBEe0 the EISA-to-PCI Line Buffers are disabled

and when ELBEe1 the EISA-to-PCI Line Buffers are enabled After PCIRST

the Line Buffers are

disabled (ELBEe0) Note that when ELBE is set to 1 the line buffers are utilized for transfers to or

from the regions defined by the REG 41 bits in the EPMRA register (offset 5Ch)

Interrupt Acknowledge Enable (IAE)

When IAEe0 the PCEB decodes PCI interrupt acknowledge

cycles in a semi-subtractive manner When there is data posted in the Line Buffers the PCEB

intervenes in the PCI interrupt acknowledge cycle by generating a retry The PCEB also initiates a

buffer flush operation and will keep generating retries until the buffers are flushed The PCEB then

subtractively decodes the PCI interrupt acknowledge cycle in order to allow an external PCI-based

interrupt controller to respond with the vector If no external PCI-based interrupt controller has

responded to the PCI Interrupt Acknowledge cycle at the DEVSEL

sampling point the cycle is

handled by the PCEB in a subtractive decode manner

When IAEe1 the PCEB positively decodes the interrupt acknowledge cycles and responds to the

cycles in the normal fashion (ie uses the PEREQ

INTA

signal to fetch the vector from the ESC

after the internal buffers are flushed)

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