82375EB datasheet(17/131 Pages) INTEL

17 / 131 page

82375EBSB

Pin Name

Type

Description

IDSEL

INITIALIZATION DEVICE SELECT

IDSEL is used as a chip select during

configuration read and write transactions The PCEB samples IDSEL during the

address phase of a transaction If the PCEB samples IDSEL asserted during a

configuration read or write the PCEB responds by asserting DEVSEL

on the next

cycle

DEVSEL

sts

DEVICE SELECT

The PCEB asserts DEVSEL

to claim a PCI transaction as a result

of positive or subtractive decode As an output the PCEB asserts DEVSEL

when it

samples IDSEL asserted during configuration cycles to PCEB configuration registers

As an input DEVSEL

indicates the response to a PCEB-initiated transaction The

PCEB when not a master samples this signal for all PCI transactions to decide

whether to subtractively decode the cycle (except for configuration and special cycles)

During reset this signal is tri-stated

PAR

PARITY

PAR is even parity across AD 310 and CBE 30

When acting as a

master the PCEB drives PAR during the address and write data phases As a target

the PCEB drives PAR during read data phases

When PCIRST

is asserted the PCEB drives the PAR signal to keep it from floating

The PCEB acts as the central resource responsible for driving the PAR signal when no

other device is granted the PCI Bus and the bus is idle

Note that the driving and tri-stating of the PAR signal is always one clock delayed from

the corresponding driving and tri-stating of the AD 310 and CBE 30

signals

PERR

sts

PARITY ERROR

PERR

reports data parity errors on all transactions except special

cycles This signal can only be asserted (by the agent receiving data) two clocks

following the data (which is one clock following the PAR signal that covered the data)

The duration of PERR

is one clock for each data phase that a data parity error is

detected (If multiple data errors occur during a single transaction the PERR

signal is

asserted for more than a single clock) PERR

must be driven high for one clock

before being tri-stated During reset this signal is tri-stated

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