82375EB datasheet(38/131 Pages) INTEL

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82375EBSB

3115 EADC1EISA ADDRESS DECODE CONTROL 1 REGISTER

Address Offset

48 – 49h

Default value

0001h

Attribute

ReadWrite

Size

16 bits

This 16-bit register specifies EISA-to-PCI mapping of the 0-1 MByte memory address range For each bit

position the memory block is enabled if the corresponding bite1 and is disabled if the bite0 EISA or DMA

memory cycles to the enabled blocks result in the EISA cycle being forwarded to the PCI Bus For disabled

memory blocks the EISA memory cycle is not forwarded to the PCI Bus

Bit

Description

880 – 896 KBytes Memory Enable

EISA-to-PCI mapping for this memory space is enabled when this

bit is 1 and disabled when this bit is 0

864 – 880 KBytes Memory Enable

EISA-to-PCI mapping for this memory space is enabled when this

bit is 1 and disabled when this bit is 0

848 – 864 KBytes Memory Enable

EISA-to-PCI mapping for this memory space is enabled when this

bit is 1 and disabled when this bit is 0

832 – 848 KBytes Memory Enable

EISA-to-PCI mapping for this memory space is enabled when this

bit is 1 and disabled when this bit is 0

816 – 832 KBytes Memory Enable

EISA-to-PCI mapping for this memory space is enabled when this

bit is 1 and disabled when this bit is 0

800 – 816 KBytes Memory Enable

EISA-to-PCI mapping for this memory space is enabled when this

bit is 1 and disabled when this bit is 0

784 – 800 KBytes Memory Enable

EISA-to-PCI mapping for this memory space is enabled when this

bit is 1 and disabled when this bit is 0

768 – 784 KBytes Memory Enable

EISA-to-PCI mapping for this memory space is enabled when this

bit is 1 and disabled when this bit is 0

Reserved

640 – 768 KBytes VGA Memory Enable

EISA-to-PCI mapping for this memory space is enabled

when this bit is 1 and disabled when this bit is 0

512 – 640 KBytes Memory Enable

EISA-to-PCI mapping for this memory space is enabled when this

bit is 1 and disabled when this bit is 0

0 – 512 KBytes Memory Enable

EISA-to-PCI mapping for this memory space is enabled when this bit

is 1 and disabled when this bit is 0

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