82375EB datasheet(39/131 Pages) INTEL

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82375EBSB

3116 IORTISA IO RECOVERY TIMER REGISTER

Address Offset

4Ch

Default Value

Attribute

ReadWrite

Size

8 bits

The IO recovery logic is used to guarantee a minimum amount of time between back-to-back 8-bit and 16-bit

PCI-to-ISA IO slave accesses These minimum times are programmable

The IO recovery mechanism in the PCEB is used to add recovery delay between PCI-originated 8-bit and 16-

bit IO cycles to ISA devices The delay is measured from the rising edge of the EISA command signal

(CMD ) to the falling edge of the next EISA command The delay is equal to the number of EISA Bus clocks

(BCLKs) that correspond to the value contained in bits 10 for 16-bit IO devices and in bits 53 for 8-bit IO

devices Note that no additional delay is inserted for back-to-back IO ‘‘sub-cycles’’ generated as a result of

byte assembly or disassembly This register defaults to 8- and 16-bit recovery enabled with two clocks of IO

recovery

Bit

Description

Reserved

Bit IO Recovery Enable

This bit enables the recovery times programmed into bits 0 and 1 of this

to 0 recovery times are disabled

8-Bit IO Recovery times

This 3-bit field defines the recovery times for 8-bit IO Programmable

delays between back-to-back 8-bit PCI cycles to ISA IO slaves is shown in terms of EISA clock cycles

(BCLK) The selected delay programmed into this field is enableddisabled via bit 6 of this register

Bits 53

BCLK

001

010

011

100

101

110

111

000

16-Bit IO Recovery Enable

This bit enables the recovery times programmed into bits 0 and 1 of this

is set to 0 recovery times are disabled

16-Bit IO Recovery Times

This 2-bit field defines the Recovery time for 16-bit IO Programmable

delays between back-to-back 16-bit PCI cycles to ISA IO slaves is shown in terms of EISA clock

cycles (BCLK) The selected delay programmed into this field is enableddisabled via bit 2 of this

Bits 10 B

CLK

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