82375EB datasheet(5/131 Pages) INTEL

номер детали	82375EB

подробное описание детали	PCI-EISA BRIDGE (PCEB)

PDF	131 Pages

Scroll/Zoom	100%

производитель	INTEL [Intel Corporation]

домашняя страница	http://www.intel.com

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5 / 131 page

CONTENTS

PAGE

5129 Memory Read Line

51210 Memory Write And Invalidate

513 PCI TRANSFER BASICS

5131 Turn-Around-Cycle Definition

5132 Idle Cycle Definition

514 BASIC READ

515 BASIC WRITE

516 CONFIGURATION CYCLES

517 INTERRUPT ACKNOWLEDGE CYCLE

518 EXCLUSIVE ACCESS

519 DEVICE SELECTION

5110 TRANSACTION TERMINATION

51101 Master Initiated Termination

51102 Target Initiated Termination

51103 PCEB Target Termination Conditions

51104 PCEB Master Termination Conditions

51105 PCEB ResponsesResults Of Termination

5111 PCI DATA TRANSFERS WITH SPECIFIC BYTE ENABLE COMBINATIONS

52 PCI Bus Latency

521 MASTER LATENCY TIMER (MLT)

522 INCREMENTAL LATENCY MECHANISM

53 PCI Bus Parity Support And Error Reporting

531 PARITY GENERATION AND CHECKING

5311 Address Phase

5312 Data Phase

532 PARITY ERRORPERR

SIGNAL

533 SYSTEM ERRORS

54 PCI Bus Arbitration

541 PCI ARBITER CONFIGURATION

5411 Fixed Priority Mode

5412 Rotating Priority Mode

5413 Mixed Priority Mode

5414 Locking Masters

542 ARBITRATION SIGNALING PROTOCOL

5421 REQ

and GNT

Rules

5422 Back-to-Back Transactions

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