82375EB datasheet(30/131 Pages) INTEL

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82375EBSB

313 PCICMDPCI COMMAND REGISTER

Address Offset

04 – 05h

Default Value

0007h

Attribute

ReadWrite Read Only

Size

16 bits

This 16-bit register contains PCI interface control information This register enablesdisables PCI parity error

checking enablesdisables PCEB bus master capability and enablesdisables the PCEB to respond to PCI-

originated memory and IO cycles Note that for certain PCI functions that are not implemented within the

PCEB the control bits are still shown (labeled ‘‘not supported’’)

Bit

Description

159

Reserved

SERR

Enable (SERRE)Not SupportedRO

Function of this bit is to control the SERR

signal

Since the PCEB does not implement the SERR

signal this bit always reads as 0 (disabled)

Wait State Control (WSC)Not SupportedRO

This bit controls insertion of wait-states for

devices that do not meet the 33-10 PCI specification Since PCEB meets the 33-10 specification this

control function is not implemented WSC is always read as 0

Parity Error Enable (PERRE)RW

PERRE controls the PCEB’s response to PCI parity errors

When PERREe1 the PCEB asserts the PERR

signal when a parity error is detected When

PERREe0 the PCEB ignores any parity errors that it detects After PCIRST

PERREe0 (parity

checking disabled)

VGA Palette Snoop (VGPS)Not SupportedRO

This bit is intended only for specific control of

PCI-based VGA devices and it is not applicable to the PCEB This bit is not implemented and always

reads as 0

Memory Write and Invalidate Enable (MWIE)Not SupportedRO

This is an enable bit for using

the Memory Write and Invalidate command The PCEB doesn’t support this command as a master

As a slave the PCEB aliases this command to a memory write This bit always reads as 0 (disabled)

Special Cycle Enable (SCE)Not SupportedRO

Since this capability is not implemented the

PCEB does not respond to any type of special cycle This bit always reads as 0

Bus Master Enable (BME)RW

ME enablesdisables the PCEB’s PCI Bus master capability

When BMEe0 the PCEB bus master capability is disabled This prevents the PCEB from requesting

the PCI Bus on behalf of EISAISA masters the DMA or the Line Buffers When BMEe1 the bus

master capability is enabled This bit is set to 1 after PCIRST

Memory Space Enable (MSE)RW

This bit enables the PCEB to accept PCI-originated memory

cycles When MSEe1 the PCEB responds to PCI-originated memory cycles to the EISA Bus When

MSEe0 the PCEB does not respond to PCI-originated memory cycles to the EISA Bus (DEVSEL

inhibited) This bit is set to 1 (enabled for BIOS access) after PCIRST

IO Space Enable (IOSE)RW

This bit enables the PCEB to accept PCI-originated IO cycles

When IOSEe1 the PCEB responds to PCI-originated IO cycles When IOSEe0 the PCEB does

not respond to a PCI IO cycle (DEVSEL

is inhibited) including IO cycles bound for the EISA Bus

This bit is set to 1 (IO space enabled) after PCIRST

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