82375EB datasheet(40/131 Pages) INTEL

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82375EBSB

3117 MAR1MEMCS

ATTRIBUTE REGISTER

Address Offset

54h

Default Value

00h

Attribute

ReadWrite

Size

8 bits

RERead Enable

When the RE bit (bit 6 4 2 0) is set to a 1 the PCEB generates MEMCS

for PCI master

DMA or EISA master memory read accesses to the corresponding segment in main memory When the RE bit

is set to a 0 the PCEB does not generate MEMCS

for PCI master DMA or EISA master memory read

accesses to the corresponding segment When the RE and WE bits are both 0 (or bit 4 in the MEMCS

Control Register is set to a 0-disabled) the PCI master DMA or EISA master can not access the correspond-

ing segment in main memory

WEWrite Enable

When the WE bit (bit 7 5 3 1) is set to a 1 the PCEB generates MEMCS

for PCI

master DMA or EISA master memory write accesses to the corresponding segment in main memory When

this bit is set to a 0 the PCEB does not generate MEMCS

for PCI master DMA or EISA master memory

write accesses to the corresponding segment When the RE and WE bits are both 0 (or bit 4 in the MEMCS

Control Register is set to a 0-disabled) the PCI master DMA or EISA master can not access the correspond-

ing segment in main memory

Bit

Description

0CC000 – 0CFFFFh Add-on BIOS WE

1eEnable 0eDisable

0CC000 – 0CFFFFh Add-on BIOS RE

1eEnable 0eDisable

0C8000 – 0CBFFFh Add-on BIOS WE

1eEnable 0eDisable

0C8000 – 0CBFFFh Add-on BIOS RE

1eEnable 0eDisable

0C4000 – 0C7FFFh Add-on BIOS WE

1eEnable 0eDisable

0C4000 – 0C7FFFh Add-on BIOS RE

1eEnable 0eDisable

0C0000 – 0C3FFFh Add-on BIOS WE

1eEnable 0eDisable

0C0000 – 0C3FFFh Add-on BIOS RE

1eEnable 0eDisable

3118 MAR2MEMCS

ATTRIBUTE REGISTER

Address Offset

55h

Default Value

00h

Attribute

ReadWrite

Size

8 bits

RERead Enable

When the RE bit (bit 6 4 2 0) is set to a 1 the PCEB generates MEMCS

for PCI master

DMA or EISA master memory read accesses to the corresponding segment in main memory When this bit is

set to a 0 the PCEB does not generate MEMCS

for PCI master DMA or EISA master memory read

accesses to the corresponding segment When the RE and WE bits are both 0 (or bit 4 in the MEMCS

Control Register is set to a 0-disabled) the PCI master DMA or EISA master can not access the correspond-

ing segment in main memory

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