82375EB datasheet(31/131 Pages) INTEL

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82375EBSB

314 PCISTSPCI STATUS REGISTER

Address Offset

06 – 07h

Default Value

0200h

Attribute

Read Only ReadWrite Clear

Size

16 bits

This 16-bit register provides status information for PCI Bus-related events Some bits are readwrite clear

These bits are set to 0 whenever the register is written and the data in the corresponding bit location is 1 (R

WC) For example to clear bit 12 and not affect any other bits write the value 0001

0000

0000b to

this register Note that for certain PCI functions that are not implemented in the PCEB the control bits are still

shown (labeled ‘‘not supported’’)

Bit

Description

Parity Error Status (PERRS)RWC

This bit is set to 1 whenever the PCEB detects a parity error

even if parity error handling is disabled (as controlled by bit 6 in the PCI Command Register)

Software sets PERRS to 0 by writinga1to this bit location

SERR

Status (SERRS)Not Supported

This bit is used to indicate that a PCI device asserted the

SERR

signal The PCEB does not implement this signal SERRS is always read as 0

Master Abort Status (MA)RWC

When the PCEB as a master generates a master abort this bit

is set to 1 Software sets MA to 0 by writinga1to this bit location

Received Target Abort Status (RTAS)RWC

When the PCEB as a master receives a target

abort condition this bit is set to 1 Software sets RTAS to 0 by writinga1to this bit location

Signaled Target Abort Status (STAS)Not Supported

This bit is set to 1 by a PCI target device

when they generate a Target Abort Since the PCEB never generates a target abort this bit is not

implemented and will always be read as a 0

109

DEVSEL Timing Status (DEVT)RO

This read only field indicates the timing of the DEVSEL

signal when PCEB responds as a target The PCI Specification defines three allowable timings for

assertion of DEVSEL

00befast 01bemedium and 10beslow (11b is reserved) DEVT indicates

the slowest time that a device asserts DEVSEL

for any bus command except configuration read

and configuration write cycles The PCEB implements medium speed DEVSEL

timing and

therefore DEVT 109 e01 when read

Reserved

315 RIDREVISION IDENTIFICATION REGISTER

Address Offset

08h

Default Value

03h (82375EB A-2 stepping)

04h (82375SB B-0 stepping)

Attribute

Read Only

Size

8 bits

This 8-bit register contains the device revision number of the PCEB Writes to this register have no effect

Bit

Description

Revision Identification Number

This 8-bit value is the revision number of the PCEB

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