SC28L201 datasheet(14/110 Pages) NXP

14 / 110 page

9397 750 13138

Product data sheet

Rev. 01 — 31 October 2005

14 of 110

Philips Semiconductors

SC28L201

3.3 V, 5 V UART, 3.125 Mbit/s, with 256-byte FIFO

When operating in the 86xxx mode, DACKN is not generated. Data is written on the

termination of CEN or WRN, whichever one occurs ﬁrst. Read data is presented from the

leading edge of the read condition (CEN and RDN both LOW).

In the 68000 mode, data is written to the registers on the rise of CEN or the fall of DACKN,

whichever one occurs ﬁrst. Data on a read cycle will become valid with respect to the fall

of CEN. It will always be valid at the fall of DACKN. The bus returns to high-impedance

when either CEN or RDN returns to a logical 1 (HIGH).

7.1.2 IACKN cycle, update CIR

(Valid for both interrupt and polled service modes.)

When the host CPU responds to the interrupt, it will usually assert the IACKN signal LOW.

This will cause the intelligent interrupt system of the UART to generate an IACKN cycle in

which the condition of the interrupting source is determined. When IACKN asserts, the

last valid of the interrupt arbitration cycle is captured in the CIR. The value captured

presents all of the important details of the highest priority interrupt at the moment the

IACKN (or the Update CIR command) was asserted. Due to system interrupt latency the

interrupt condition captured by the CIR may not be the condition that caused the initial

assertion of the interrupt. Recall that any number of interrupts can occur at the same time.

Nearly all interrupt events are totally asynchronous to each other and will depend on a

variety of internal or external clocks with various times or being enabled or disabled.

The UART will respond to the IACKN cycle with an interrupt vector. The interrupt vector

may be a ﬁxed value, the content of the Interrupt Vector Register, or when interrupt vector

modiﬁcation is enabled via ICR, it may contain codes for the interrupt type and/or

interrupting channel. This allows the interrupt vector to steer the interrupt service directly

to the proper service routine. The interrupt value captured in the CIR remains until another

IACKN or Update CIR command is given to the UART. The interrupting channel and

interrupt type ﬁelds of the CIR set the current interrupt context of the UART. The channel

component of the interrupt context allows the use of Global Interrupt Information registers

that appear at ﬁxed positions in the register address map. For example, a read of the

Global GIBCR will read the channel FIFO byte count if the CIR interrupt context is the

receiver. At another time read of the GIBCR will show the transmitter byte count if the

interrupt context is that of the transmitter interrupt, and so on. Global registers exist to

facilitate qualifying the interrupt parameters and for writing to and reading from FIFOs

without explicitly addressing them. They are essentially an indirect address to the content

of the CIR.

The CIR will load with 0x00 if IACKN or Update CIR is asserted when the arbitration circuit

is not asserting an interrupt. In this condition there is no arbitration value that exceeds the

threshold value. When Interrupt vector modiﬁcation is active in this situation the interrupt

vector bits associated with the CIR will all be zero. A zero type ﬁeld indicates nothing with

in the UART is requiring processor service.

Remark: IACKN is essentially a special read action where the value of the interrupt vector

is presented to the data bus.

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