SC28L201 datasheet(23/110 Pages) NXP

23 / 110 page

9397 750 13138

Product data sheet

Rev. 01 — 31 October 2005

23 of 110

Philips Semiconductors

SC28L201

3.3 V, 5 V UART, 3.125 Mbit/s, with 256-byte FIFO

The ‘change of break’ means that either a break has been detected or that the break

condition has been cleared. This bit is available in the ISR. The break change bit being set

in the ISR and the received break bit being set in the SR will signal the beginning of a

break. At the termination of the break condition only the change of break in the ISR will be

set. After the break condition is detected the termination of the break will only be

recognized when the RXD input has returned to the HIGH state for two successive edges

of the 1

× clock; 1⁄

2-bit to 1-bit time (see above).

The receiver is disabled by reset or via CR commands. A disabled receiver will not

interrupt the host CPU under any circumstance in the normal mode of operation. If the

receiver is in the multi-drop or special mode, it will be partially enabled and thus may

cause an interrupt. Refer to Section 8.2.2 “Mode Register 1 (MR1)” for more information.

7.4.7.4

Receiver FIFO

The receiver buffer memory is a 256-byte FIFO with three status bits appended to each

data byte. (The FIFO is then 256 11-bit ‘words’.) The receiver state machine gathers the

bits from the Receiver Shift Register and the status bits from the receiver logic and writes

the assembled byte and status bits to the RxFIFO shortly after the stop bit has been

sampled. Logic associated with the FIFO encodes the number of ﬁlled positions for

presentation to the interrupt arbitration system. The encoding is always the number of

ﬁlled positions. Thus, a full RxFIFO will bid with the value of 255 and the Status Register

RxFULL bit is set. The RxFULL bit means 256 characters. When empty, it will not bid at

all. One position occupied bids with the value ‘1’. An empty FIFO will not bid since no

character is available.

Normally RxFIFO will present a bid to the arbitration system whenever it has one or more

ﬁlled positions. The bits of the RxFIFO Interrupt Offset Level (RxFIL) of MR0 allow the

user to modify this characteristic so that bidding will not start until one of four levels has

been reached.

As will be shown later, this feature may be used to make slight improvements in the

interrupt service efﬁciency. A similar system exists in the transmitter.

7.4.7.5

RxFIFO status bits, status reporting modes

This description applies to the upper three bits in the Status Register. These three bits are

not ‘in the status register’; they are part of the RxFIFO. The three status bits at the output

of the RxFIFO are presented as the upper three bits of the Status Register.

The error status of a character, as reported by a read of the SR (status register upper

three bits) can be provided in two ways, as programmed by the error mode control bit in

the mode register: Character mode or the Block mode. The Block mode may be further

modiﬁed (via a CR command) to set the status bits as the characters enter the FIFO or as

they are read from the FIFO.

In the Character mode, status is provided on a character-by-character basis as the

characters are read from the RxFIFO: the ‘status’ applies only to the character at the

output of the RxFIFO (the next character to be read).

In the Block mode (on entry), the status provided in the SR for these three bits is the

logical OR of the status for all characters coming to the input of the RxFIFO since the last

reset error command was issued. In this mode each of the status bits stored in the

RxFIFO are passed through a latch as they are sequentially written to the receiver FIFO. If

any of the characters has an error bit set that latch will set and remain set until it is reset

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