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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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SC28L201 датащи(PDF) 65 Page - NXP Semiconductors |
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SC28L201 датащи(HTML) 65 Page - NXP Semiconductors |
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65 / 110 page  9397 750 13138 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 — 31 October 2005 65 of 110 Philips Semiconductors SC28L201 3.3 V, 5 V UART, 3.125 Mbit/s, with 256-byte FIFO 8.4.3 Counter/Timer clock source (CTCS0 and CTCS1) Remark: Writing to this register removes the control established in the counter/timer portion of the ACR in the default register map. Table 40: CTCS0 and CTCS1 - Counter/Timer clock source registers (address 0x24, 0x2C) bit description Bit Symbol Description 7:6 reserved 5:4 Mode control 00 = selects Counter mode. Generates a timing edge. 01 = selects Timer mode. Generates a square wave. 10 = reserved 11 = selects Timer Pulse mode. Generates periodic pulses twice the frequency as in Timer mode. Pulse width is one cycle of the clock as it is delivered to the C/T, that is, after any prescale. 3:0 Clock selection 0000 = external I/O2A (for CT 0); I/O7A (for CT 1) 0001 = external I/O2A/16 (for CT 0); I/O7A/16 (for CT 1) 0010 = SCLK 0011 = SCLK/2 0100 = SCLK/16 0101 = SCLK/32 0110 = SCLK/64 0111 = SCLK/128 1000 = TxCA1X 1001 = reserved 1010 = reserved 1011 = reserved 1100 = Rx Character Count (Ch A) Clock is RxFIFO A load pulse 1101 = reserved 1110 = reserved 1111 = reserved |
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