SC28L201 datasheet(95/110 Pages) NXP

95 / 110 page

9397 750 13138

Product data sheet

Rev. 01 — 31 October 2005

95 of 110

Philips Semiconductors

SC28L201

3.3 V, 5 V UART, 3.125 Mbit/s, with 256-byte FIFO

[1]

Test conditions for outputs: CL = 85 pF, except interrupt outputs. Test conditions for interrupt outputs: CL =85pF, RL = 2.7 kΩ to VDD.

[2]

Timing is illustrated and referenced to the WRN and RDN inputs. Also, CEN may be the ‘strobing’ input. CEN and RDN (also CEN and

WRN) are ORed internally. The signal asserted last initiates the cycle and the signal negated ﬁrst terminates the cycle.

[3]

Guaranteed by characterization of sample units.

[4]

If CEN is used as the ‘strobing’ input, the parameter deﬁnes the minimum HIGH times between one CEN and the next. The RDN signal

must be negated for td(RWD) time to guarantee that any Status Register changes are valid.

[5]

Minimum frequencies are not tested, but are guaranteed by design.

[6]

Clocks for 1

× mode should be reasonably symmetrical.

[7]

Data is usually setup with respect to CEN going LOW (the leading edge of CEN). This mode strongly implies the use of DACKN. (Its use

is not strictly required.) DACKN is derived from the X1/SCLK input. It is seldom that the system clocks that ultimately drive the CEN,

address, and R/WN signals are synchronous to the X1/SCLK. If address, data, R/WN are setup before CEN goes LOW and hold

through DACKN, the timing parameters above will be guaranteed.

th(D)(mot)

CEN HIGH to data hold time

0-0-

tsu(An-CENL)(mot)

address to CEN LOW setup

time

10-10-

th(CENL-An)(mot)

CEN LOW to address hold time

tDv(CENL)

CEN LOW to data valid time

td(RWD)(mot)

read and write cycle HIGH time

[2] [4]

10-10-

tDCR

X1/SCLK HIGH to DACKN LOW

time (read cycle)

tDCW

X1/SCLK HIGH to DACKN LOW

time (write cycle)

tDAT

CEN to IACKN HIGH DACKN

high-impedance time

tCSC

CEN or IACKN to X1/SCLK

HIGH setup time

for minimum DACKN cycle

Table 82:

Dynamic characteristics …continued

Tamb = −40 °C to +85 °C; voltage tolerance ± 10 %; unless otherwise speciﬁed. [1]

Symbol

Parameter

Conditions

VDD = 3.3 V

VDD =5V

Unit

Min

Max

Min

Max

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