SC28L201 datasheet(8/110 Pages) NXP

8 / 110 page

9397 750 13138

Product data sheet

Rev. 01 — 31 October 2005

8 of 110

Philips Semiconductors

SC28L201

3.3 V, 5 V UART, 3.125 Mbit/s, with 256-byte FIFO

Table 3:

Pin description for 68000 bus interface (Motorola)

See Figure 4.

Symbol

Type

Description

MODE_IM

Bus conﬁguration. When LOW, conﬁgures the bus interface to the conditions

shown in this table.

D0 to D7

18, 17, 16,

15, 12, 11,

10, 9

I/O

Data bus. Bidirectional 3-state data bus used to transfer commands, data and status

between the UART and the CPU. D0 is the least signiﬁcant bit.

CEN

Chip Enable. Active LOW input signal. When LOW, data transfers between the CPU

and the UART are enabled on D[0:7] as controlled by the R/WN and A6 to A0 inputs.

When HIGH, places the D[0:7] lines in the 3-state condition.

R/WN

Read/Write. Input signal. When CEN is LOW, R/WN HIGH inputs a read cycle, when

LOW a write cycle.

IACKN

Interrupt acknowledge. Active LOW input indicates an interrupt acknowledge

cycle. Usually asserted by the CPU in response to an interrupt request. When

asserted, places the interrupt vector on the bus and asserts DACKN.

DACKN

Data transfer acknowledge. An open-drain active LOW output asserted in a write,

read, or interrupt acknowledge cycle to indicate proper transfer of data between the

CPU and the UART.

A6 to A0

3, 4, 5, 6,

20, 21, 22

Address inputs. Select the UART internal registers and ports for read/write

operations.

RESETN

Reset. A LOW level clears internal registers (SR, IMR, ISR, OPR, OPCR), places

I/O[7:0] A and B at high-impedance input state, stops the counter/timer, and puts

Channel in the inactive state, with the TXD output in the ‘mark’ (HIGH) state. Sets

MR pointer to MR1 9600 baud, 1 start, no parity and 1 stop bit(s).

IRQN

Interrupt request. Active LOW, open-drain output which signals the CPU that one

or more of the eleven (11) maskable interrupting conditions are true.

X1/SCLK

Crystal 1. Crystal or external clock input. A crystal or clock of the speciﬁed limits

must be supplied at all times. When a crystal is used, a capacitor must be connected

from this pin to ground (see Figure 14).

Crystal 2. Connection for other side of the crystal. When a crystal is used, a

capacitor must be connected from this pin to ground (see Figure 12). If X1/SCLK is

driven from an external source, this pin must be open or not driving more than

2 CMOS or TTL loads.

RXD

Channel Receiver serial data input. The least signiﬁcant bit is received ﬁrst. ‘Mark’

is HIGH; ‘space’ is LOW.

TXD

Channel Transmitter serial data output. The least signiﬁcant bit is transmitted ﬁrst.

This output is held in the ‘mark’ condition when the transmitter is disabled, idle or

when operating in local loopback mode. ‘Mark’ is HIGH; ‘space’ is LOW.

I/O7A to I/O0A

37, 38, 39,

40, 41, 42,

43, 44

I/O

General-purpose input and output ports. The character of these pins is controlled

by I/OPCR. They may be inputs or outputs and will present many internal clocks and

interrupt signals: RTS, CTS, DTR, DSR, and so on. All have change-of-state

detectors and the input is always active. These pins are set to input only when

addressed from the low order 16 address space. When these pins are conﬁgured for

interrupt type signals (RXRDY, TXRDY, C/TRDY), they switch to open-drain outputs.

Each of these pins has a small pull-up ‘resistor’ that supplies approximately 5

µA of

current.

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