SC28L201 datasheet(57/110 Pages) NXP

57 / 110 page

9397 750 13138

Product data sheet

Rev. 01 — 31 October 2005

57 of 110

Philips Semiconductors

SC28L201

3.3 V, 5 V UART, 3.125 Mbit/s, with 256-byte FIFO

RxINT

Receiver entered the arbitration process. (Also Rx DMA hand-shake at I/O

pins.)

The general function of this bit is to indicate that the RxFIFO has data available

and that it has entered the arbitration process. The particular meaning of this bit

is programmed by RxFIL register. If programmed as receiver ready

(MR2[3:2] = 00), it indicates that at least one character has been received and

is waiting in the RxFIFO to be read by the host CPU. It is set when the

character is transferred from the receive shift register to the RxFIFO and reset

when the CPU reads the last character from the RxFIFO.

If RxFIL is programmed as FIFO full, ISR[1] is set when a character is

transferred from the receive holding register to the RxFIFO and the transfer

causes the RxFIFO to become full, that is, all 256 FIFO positions are occupied.

It is reset whenever RxFIFO is not full. If there is a character waiting in the

receive shift register because the FIFO is full, the bit is set again when the

waiting character is transferred into the FIFO.

The other two conditions of these bits, 3

⁄4 and 1⁄2 full operate in a similar

manner. The ISR[1] bit is set when the RxFIFO ﬁll level meets or exceeds the

value; it is reset when the ﬁll level is less. See the description of the MR2

Remark: This bit must be at a one (1) for the receiver to enter the arbitration

process. It is the fact that this bit is zero (0) when the RxFIFO is empty that

stops an empty FIFO from entering the interrupt arbitration. Also note that the

meaning if this bit is not quite the same as the similar bit in the Status Register

(SR).

TxINT

Transmitter entered the arbitration process. (Also Tx DMA hand-shake at I/O

pins.)

The general function of this bit is to indicate that the TxFIFO has an at least one

empty space for data. The particular meaning of the bit is controlled by MR0

[5:4] indicates the TxFIFO may be loaded with one or more characters. If

MR0[5:4] = 00 (the default condition) this bit will not set until the TxFIFO is

empty: 256 bytes available. If the ﬁll level of the TxFIFO is below the trigger

level programmed by the TxINT ﬁeld of the Mode Register 0, this bit will be set.

A one in this position indicates that at least one character can be sent to the

TxFIFO. It is turned off as the TxFIFO is ﬁlled above the level programmed by

MR0[5:4]. This bit turns on as the FIFO empties. (Note that the RxFIFO bit

turns on as the FIFO ﬁlls.) This often a point of confusion in programming

interrupt functions for the receiver and transmitter FIFOs.

Remark: This bit must be at a one (1) for the transmitter to enter the arbitration

process. It is the fact that this bit is zero (0) when the TxFIFO is full that stops a

full TxFIFO from entering the interrupt arbitration. Also note that the meaning if

this bit is not quite the same as the similar bit in the status register (SR).

Table 25:

ISR - Interrupt Status Register (address 0x25) bit description …continued

Bit

Symbol

Description

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