SC28L201 datasheet(7/110 Pages) NXP

7 / 110 page

9397 750 13138

Product data sheet

Rev. 01 — 31 October 2005

7 of 110

Philips Semiconductors

SC28L201

3.3 V, 5 V UART, 3.125 Mbit/s, with 256-byte FIFO

RDN

Read strobe. When LOW and CEN is also LOW, causes the contents of the

addressed register to be presented on the data bus. The read cycle begins on the

falling edge of RDN.

A6 to A0

3, 4, 5, 6,

20, 21, 22

Address inputs. Select the UART internal registers and ports for read/write

operations.

RESET

Reset. A HIGH level clears internal registers (SR, IMR, ISR, OPR, OPCR), places

I/O[7:0] at high-impedance input state, stops the counter/timer, and puts Channel in

the inactive state, with the TXD output in the ‘mark’ (HIGH) state. Sets MR pointer to

MR1 9600 baud, 1 start, no parity and 1 stop bit(s).

IRQN

Interrupt request. Active LOW, open-drain output which signals the CPU that one

or more of the eleven (11) maskable interrupting conditions are true.

IACKN

Interrupt acknowledge. Active LOW input indicates an interrupt acknowledge

cycle. Usually asserted by the CPU in response to an interrupt request. When

asserted places the interrupt vector on the bus.

X1/SCLK

Crystal 1. Crystal or external clock input. A crystal or clock of the speciﬁed limits

must be supplied at all times. When a crystal is used, a capacitor must be connected

from this pin to ground (see Figure 12).

Crystal 2. Connection for other side of the crystal. When a crystal is used, a

capacitor must be connected from this pin to ground (see Figure 12). If X1/SCLK is

driven from an external source, this pin must be open or not driving more than

2 CMOS or TTL loads.

RXD

Channel A Receiver serial data input. The least signiﬁcant bit is received ﬁrst.

‘Mark’ is HIGH; ‘space’ is LOW.

TXD

Channel A Transmitter serial data output. The least signiﬁcant bit is transmitted

ﬁrst. This output is held in the ‘mark’ condition when the transmitter is disabled, idle

or when operating in local loopback mode. ‘Mark’ is HIGH; ‘space’ is LOW.

I/O7A to I/O0A

37, 38, 39,

40, 41, 42,

43, 44

I/O

General-purpose input and output ports. The character of these pins is controlled

by I/OPCR. They may be inputs or outputs and will present many internal clocks and

interrupt signals: RTS, CTS, DTR, DSR, and so on. All have change-of-state

detectors and the input is always active. These pins are set to input only when

addressed from the low order address space. When these pins are conﬁgured for

interrupt type signals (RXRDY, TXRDY, C/TRDY), they switch to open-drain outputs.

Each of these pins has a small pull-up ‘resistor’ that supplies approximately 5

µA of

current.

I/O6B

I/O

Additional general-purpose I/O pins. They are similar to the above without any

connection to the data path or clocks. They have Change-Of-State (COS) detectors

and will generate interrupts if enabled. Each of these pins has a small pull-up

‘resistor’ that supplies approximately 5

µA of current.

I/O4B to I/O2B

30, 31, 32

I/O0B

VDD

1, 13, 24,

power

Power supply (4 pins). +3.3 V

± 10 % or +5.0 V ± 10 % supply input. Operation is

assured from 2.97 V or 5.5 V. Timing parameters are speciﬁed with respect to the

VDD being at 3.3 V ± 10 % or 5.0 V ± 10 %.

VSS

2, 14, 25,

35, 36

power

Ground (5 pins)

Table 2:

Pin description for 80xxx bus interface (Intel) …continued

See Figure 3.

Symbol

Type

Description

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