SC28L201 datasheet(31/110 Pages) NXP

31 / 110 page

9397 750 13138

Product data sheet

Rev. 01 — 31 October 2005

31 of 110

Philips Semiconductors

SC28L201

3.3 V, 5 V UART, 3.125 Mbit/s, with 256-byte FIFO

For example: The break condition is sometimes used to signal a starting point in a

continuous stream of data. A Continuous running weather report or stock market

‘ticker-tape’ report needs breaks in the data so that a receiver knows where the data

starts. Once start of the break is detected it is important to reset the ‘change of break’

interrupt so that this bit can signal the condition of the break ending. This is signaled by

the SC28L201 the setting another change of break event in the ISR. Since it is assumed

the data will be starting very soon after the end of break it is important to give the change

of break condition a high priority. This may be accomplished by setting the arbitration

value for the ‘change of break’ to a high value. The value in the ‘change of break

programmable ﬁeld’ in Table 4 would be 0x7F.

7.4.8.4

IACKN cycle, update CIR

When the host CPU responds to the interrupt, it will usually assert the IACKN signal LOW.

This will cause the UART to generate an IACKN cycle in which the condition of the

interrupting device is determined. When IACKN asserts, the last valid interrupt number is

captured in the CIR. The value captured presents most of the important details of the

highest priority interrupt at the moment the IACKN (or the ‘Update CIR’ command) was

asserted.

The UART will respond to the IACKN cycle with an interrupt vector. The interrupt vector

may be a ﬁxed value, the content of the Interrupt Vector Register, or when ‘Interrupt Vector

Modiﬁcation’ is enabled via ICR, it may contain codes for the interrupt type and/or

interrupting channel. This allows the interrupt vector to steer the interrupt service directly

to the proper service routine. The interrupt value captured in the CIR remains until another

IACKN cycle occurs or until an ‘Update CIR’ command is given to the UART. The

interrupting channel and interrupt type ﬁelds of the CIR set the current ‘interrupt context’

of the UART.

The CIR drives the several Global Interrupt Information registers that appear at ﬁxed

positions in the register address map. For example, a read of the Global Byte Count return

the value of the FIFO ﬁll level of the receiver or transmitter depending on which one is

interrupting. Global registers exist to facilitate qualifying the interrupt parameters and for

writing to and reading from FIFOs without explicitly addressing them. They are essentially

indirect addresses to characteristics of the interrupting source.

The CIR will load with 0x00 if IACKN or Update CIR is asserted when the arbitration circuit

is not asserting an interrupt. In this condition there is no arbitration value that exceeds the

threshold value. When Interrupt vector modiﬁcation is active in this situation the interrupt

vector bits associated with the CIR will all be zero.

7.4.8.5

Global registers

The Global Registers, 10 in all, are driven by the interrupt system. They are deﬁned by the

content of the CIR (Current Interrupt Register) as a result of an interrupt arbitration. In

other words they are indirect registers pointed to by the content of the CIR. The list of

global register follows:

• GIBCR: the byte count of the interrupting FIFO

• GICR: channel number of the interrupting channel

The GCIR will read 0 except for Counter/Timer 1 and I/O[n]B pins

• GITR: type identiﬁcation of interrupting channel

• GRxFIFO: pointer to the interrupting receiver FIFO

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