SC28L201 datasheet(71/110 Pages) NXP

71 / 110 page

9397 750 13138

Product data sheet

Rev. 01 — 31 October 2005

71 of 110

Philips Semiconductors

SC28L201

3.3 V, 5 V UART, 3.125 Mbit/s, with 256-byte FIFO

Else the interrupt is another type, speciﬁed in CIR[5:1].

Remark: The GIBCR, Global Interrupting Byte Count Register, may be read to determine

an exact character count.

8.5.4 Interrupt Vector Register (IVR)

The IVR contains the byte that will be placed on the data bus during an IACKN cycle when

the GCCR bits [2:1] are set to binary ‘01’. This is the unmodiﬁed form of the interrupt

vector.

8.5.5 Global Interrupting Channel Register (GICR)

A register associated with the interrupting channel as deﬁned in the CIR. It contains the

channel number for the interrupting channel.

8.5.6 Global Interrupting Byte Count Register (GIBCR)

A register associated with the interrupting channel as deﬁned in the CIR. Its numerical

value equals TxEL or RxFL at the time IACKN or ‘Update CIR’ command was issued. The

true number of bytes ready for transfer to the transmitter or transfer from the receiver. It is

undeﬁned for other types of interrupts.

Table 49:

IVR - Interrupt Vector Register (address 0x64) bit description

Bit

Symbol

Description

7:0

8 data bits of the Interrupt Vector (IVR)

Table 50:

GICR - Global Interrupting Channel Register (address 0x70) bit description

Bit

Symbol

Description

7:1

reserved

Channel code

0=a

1 = reserved

Table 51:

GIBCR - Global Interrupting Byte Count Register (address 0x71) bit description

Bit

Symbol

Description

7:0

Channel byte count code

0000 0001 = 1

0000 0010 = 2

…

1111 1111 = 255

0000 0000 = 256

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