SC28L201 datasheet(49/110 Pages) NXP

49 / 110 page

9397 750 13138

Product data sheet

Rev. 01 — 31 October 2005

49 of 110

Philips Semiconductors

SC28L201

3.3 V, 5 V UART, 3.125 Mbit/s, with 256-byte FIFO

[1]

If this bit is not ‘0’, the characters will be stripped regardless of bits [3:2] or [1:0].

8.2.5 Receiver Clock Select Register (RxCSR) and Transmitter Clock Select

Both registers consist of single 6-bit ﬁeld that selects the clock source for the receiver and

transmitter respectively. During a read the unused bits in this register read ‘000’. The

‘BRG’ baud rates (ﬁxed BRG rates) shown in Table 21 are based on the SCLK crystal

frequency of 14.7456 MHz. The baud rates shown in Table 21 will vary as the SCLK

crystal clock varies. For example, if the SCLK rate is changed to 7.3728 MHz all the rates

below will reduce by 1

⁄

1:0

Address Recognition control.

00 = default

01 = Auto wake

10 = Auto doze

11 = Auto wake and Auto doze

This ﬁeld controls the operation of the Address recognition logic. If the device

is not operating in the special or Wake-up mode, this hardware may be used

as a general-purpose character detector by choosing any combination except

00. Interrupt generation is controlled by the channel IMR. The interrupt may be

cleared by a read of the XISR, the Xon/Xoff Interrupt Status Register. See

further description in Section 7.4.7.6 “Wake-up mode”.

Table 19:

MR3 - Mode Register 3 (address 0x23) bit description …continued

Bit

Symbol

Description

Table 20:

RxCSR - Receiver Clock Select Register (address 0x30) and

TxCSR - Transmitter Clock Select Register (address 0x31) bit description

Bit

Symbol

Description

7:6

reserved

5:0

Transmitter/Receiver Clock Select code; see Table 21.

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