SC28L201 datasheet(73/110 Pages) NXP

73 / 110 page

9397 750 13138

Product data sheet

Rev. 01 — 31 October 2005

73 of 110

Philips Semiconductors

SC28L201

3.3 V, 5 V UART, 3.125 Mbit/s, with 256-byte FIFO

8.5.10 Bidding Control Register, Break Change (BCRBRK)

This register provides the 8 MSBs of the Interrupt Arbitration number for a break change

interrupt.

8.5.11 Bidding Control Register, Change-Of-State (BCRCOS)

This register provides the 8 MSBs of the Interrupt Arbitration number for a

Change-Of-State, COS, interrupt.

8.5.12 Bidding Control Register, Xon/Xoff (BCRx)

This register provides the 8 MSBs of the Interrupt Arbitration number for an Xon/Xoff

interrupt.

8.5.13 Bidding Control Register, Address (BCRA)

This register provides the 8 MSBs of the Interrupt Arbitration number for an address

recognition event interrupt.

8.5.14 Bidding Control Register, C/T 0 and C/T 1 (BCR C/T)

This register provides the 8 MSBs of the Interrupt Arbitration number for a counter/timer

event interrupt.

8.5.15 Bidding Control Register, Received Loopback Error (BCRLBE)

This register provides the 8 MSBs of the Interrupt Arbitration number for the received

loopback error interrupt.

Table 55:

BCRBRK - Bidding Control Register, Break change (address 0x50) bit description

Bit

Symbol

Description

7:0

MSBs of break change interrupt bid.

Table 56:

BCRCOS - Bidding Control Register, Change-Of-State (address 0x51)

bit description

Bit

Symbol

Description

7:0

MSBs of Change-Of-State detectors (COS) interrupt bid.

Table 57:

BCRx - Bidding Control Register, Xon/Xoff (address 0x53) bit description

Bit

Symbol

Description

7:0

MSBs of an Xon/Xoff interrupt bid.

Table 58:

BCRA - Bidding Control Register, Address (address 0x54) bit description

Bit

Symbol

Description

7:0

MSBs of an address recognition event interrupt bid.

Table 59:

BCRA - Bidding Control Register, Address (address 0x52) bit description

Bit

Symbol

Description

7:0

MSBs of a Counter/Timer event interrupt bid.

Table 60:

BCRLBE - Bidding Control Register, Address (address 0x55) bit description

Bit

Symbol

Description

7:0

MSBs of a received loopback error event interrupt bid.

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