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SC28L201 датащи(PDF) 69 Page - NXP Semiconductors |
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SC28L201 датащи(HTML) 69 Page - NXP Semiconductors |
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69 / 110 page ![]() 9397 750 13138 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 — 31 October 2005 69 of 110 Philips Semiconductors SC28L201 3.3 V, 5 V UART, 3.125 Mbit/s, with 256-byte FIFO 8.5 Registers of the Arbitrating Interrupt system and bidding control 8.5.1 Interrupt Control Register (ICR) This register provides a single 8-bit field called the interrupt threshold for use by the interrupt arbiter. The field is interpreted as a single unsigned integer. The interrupt arbiter will not generate an external interrupt request, by asserting IRQN, unless the value of the highest priority interrupt exceeds the value of the interrupt threshold. If the highest bidder in the interrupt arbitration is lower than the threshold level set by the ICR, the Current Interrupt Register, CIR, will contain 0x00. Remark: While a Watchdog Timer interrupt is pending, the ICR is not used and only receiver codes are presented for interrupt arbitration. This allows receivers with very low count values (perhaps below the threshold value) to win interrupt arbitration without requiring the user to explicitly lower the threshold level in the ICR. 8.5.2 Update CIR (UCIR): the most important command for polled or interrupt service A write to address 0x61 data is not important. A command based upon a decode of a write to address 0x61 (UCIR is not a register). A write (the write data is not important; a ‘Don’t care’) to this ‘register’ causes the Current Interrupt Register to be updated with the value that is winning interrupt arbitration. The register would be used in systems that poll the interrupt status registers rather than wait for interrupts. Alternatively, the CIR is normally updated during an Interrupt Acknowledge Bus (IACKN) cycle in interrupt-driven systems. Table 46: ICR - Interrupt Control Register (address 0x60) bit description Bit Symbol Description 7:0 Upper 8 bits of the Arbitration Threshold Table 47: UCIR - Update CIR (address 0x61) bit description Bit Symbol Description 7:0 data not important |
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