SC28L201 datasheet(55/110 Pages) NXP

55 / 110 page

9397 750 13138

Product data sheet

Rev. 01 — 31 October 2005

55 of 110

Philips Semiconductors

SC28L201

3.3 V, 5 V UART, 3.125 Mbit/s, with 256-byte FIFO

TxRDY

Transmitter Ready.

0 = no

1 = yes

This bit, when set, indicates that the TxFIFO is ready to be loaded with at

least one more character. This bit is cleared when the TxFIFO is full or is

above its interrupt threshold level set in the MR registers or TxFIFO interrupt

Fill Level register (TxFIL). Characters loaded in the TxFIFO while the

transmitter is disabled will not be transmitted.

RxFULL

RxFIFO Full.

0 = no

1 = yes

This bit is set when a character is transferred from the Receive Shift Register

to the receive FIFO, and the transfer causes the FIFO to become full, that is,

all 256 RxFIFO positions are occupied. It is reset when the CPU reads the

RxFIFO and that read leaves one or more empty byte position(s). If a

character is waiting in the receive shift register because the RxFIFO is full,

RxFULL is not reset until the second read of the RxFIFO since the waiting

character is immediately loaded to the RxFIFO.

RxRDY

Receiver Ready.

0 = no

1 = yes

This bit indicates that a character has been received and is waiting in the

RxFIFO to be read by the CPU. It is set when the character is transferred

from the receive shift register to the RxFIFO and reset when the CPU reads

the RxFIFO, and no more characters are in the RxFIFO.

Table 24:

SR - Channel Status Register (address 0x01) bit description …continued

Bit

Symbol

Description

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