SC28L201 datasheet(46/110 Pages) NXP

46 / 110 page

9397 750 13138

Product data sheet

Rev. 01 — 31 October 2005

46 of 110

Philips Semiconductors

SC28L201

3.3 V, 5 V UART, 3.125 Mbit/s, with 256-byte FIFO

8.2.3 Mode Register 2 (MR2)

MR2 can be accessed directly at 0x22 in the Extended section of the address map, or by

means of the MR Pointer at 0x00 used by legacy code.

The MR2 register provides basic channel setup control that may need more frequent

updating.

Table 18:

MR2 - Mode Register 2 (address 0x22) bit description

Bit

Symbol

Description

7:6

Channel Mode Select. The UART can operate in one of the following four

modes:

00 = Normal mode (default)

01 = Automatic Echo mode

10 = Local loopback mode

11 = Remote loopback mode

Normal mode: the transmitter and receiver operating independently.

Automatic Echo mode: this mode automatically retransmits the received

data. The following conditions are true while in Automatic Echo mode:

• Received data is re-clocked and re-transmitted on the TXD output.

• The receiver clock is used for the transmitted data.

• The receiver must be enabled, but the transmitter need not be enabled.

• The TxRDY and Tx Idle status bits are inactive.

• The received parity is checked, but is not regenerated for transmission,

that is, transmitted parity bit is as received.

• Character framing is checked, but the stop bits are retransmitted as

received. Rx data is sent to RxFIFO.

• A received break is echoed as received until the next valid start bit is

detected.

• CPU to receiver communication continues normally, but the CPU to

transmitter link is disabled.

Local loopback mode. In this mode:

• The transmitter output is internally connected to the receiver input.

• The transmitter’s 1

× clock is used for the receiver.

• The TXD output is held HIGH.

• The RXD input is ignored.

• The transmitter must be enabled, but the receiver need not be enabled.

• CPU to transmitter and receiver communications continue normally.

Remote Loopback diagnostic mode. In this mode:

• Received data is re-clocked and re-transmitted on the TXD output.

• The receiver 1

× clock is used for the transmitted data.

• Received data is not sent to the local CPU, and the error status

conditions are inactive.

• The received parity is not checked and is not regenerated for

transmission, that is, the transmitted parity bit is as received.

• The receiver must be enabled, but the transmitter need not be enabled.

• Character framing is not checked, and the stop bits are retransmitted as

received.

• A received break is echoed as received until the next valid start bit is

detected.

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