SC28L201 datasheet(36/110 Pages) NXP

36 / 110 page

9397 750 13138

Product data sheet

Rev. 01 — 31 October 2005

36 of 110

Philips Semiconductors

SC28L201

3.3 V, 5 V UART, 3.125 Mbit/s, with 256-byte FIFO

7.4.10.7

Xon/Xoff interrupts

The Xon/Xoff logic generates interrupts only in response to recognizing either of the

characters in the XonCR or XoffCR (Xon or Xoff Character Registers). The transmitter

activity initiated by the Xon/Xoff logic or any CR command does not generate an interrupt.

The character comparators operate regardless of the value in MR3[3:2]. Hence the

comparators may be used as general-purpose character detectors by setting

MR3[3:2] = 00 and enabling the Xon/Xoff interrupt in the IMR.

The UART can present the Xon/Xoff recognition event to the interrupt arbiter for IRQN

generation. The IRQN generation may be masked by setting bit 4 of the Interrupt Mask

Control Register X, BCRx, of the channel. The interrupt status can be examined in ISR[4].

If cleared, no Xon/Xoff recognition event is interrupting. If set, an Xon or Xoff recognition

event has been detected. The X Interrupt Status Register (XISR) can be read for details of

the interrupt and to examine other, non-interrupting, status of the Xon/Xoff logic. Refer to

Section 8.3.4 “Xon/Xoff Interrupt Status Register (XISR)”.

The character recognition function and the associated interrupt generation is disabled on

hardware or software reset.

7.4.10.8

Multi-drop, Wake-up, or 9-bit mode

This mode is used to address a particular UART among a group connected to the same

serial data source. Normally it is accomplished by redeﬁning the meaning of the parity bit

such that it indicates a character as address or data. While this method is fully supported

in the SC28L201, it also supports recognition of the character itself. Upon recognition of

its address the receiver will be enabled and data loaded onto the RxFIFO.

Further, the Address recognition has the ability, if so programmed, to disable (not reset)

the receiver when an address is seen that is not recognized as its own. The particular

features of ‘Auto Wake and Auto Doze’ are described in the detailed descriptions under

Section 7.4.7 “Receiver operation”.

Remark: Care should be taken in the programming of the character recognition registers.

Programming 0x00, for example, may result in a break condition being recognized as a

control character. This will be further complicated when binary data is being processed.

7.5 Programming the host interface

The SC28L201 is designed for a very close compatibility with legacy software written for

other Philips/Signetics 2 channel UARTs. The part will initialize to the SC28L91 function.

This function is controlled in the lower 16 address positions.

A reset (both hardware and software) will return the part to this mode with the control

registers set for 9600 baud, 8 bits, no parity and one stop bit. Interrupt will be set for

Receiver Ready and transmitter Empty. Transmitters and receivers will not be enabled.

Basic operation should be obtained by a single write of 0xE0 to the Command Register.

That will enable the receiver and transmitter.

Addressing outside of the lower 16 address spaces will enable all the advanced features.

In general, before calling legacy code, advanced features should be disabled (character

stripping, for example).

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