SC28L201 datasheet(22/110 Pages) NXP

22 / 110 page

9397 750 13138

Product data sheet

Rev. 01 — 31 October 2005

22 of 110

Philips Semiconductors

SC28L201

3.3 V, 5 V UART, 3.125 Mbit/s, with 256-byte FIFO

7.4.7.3

Receiver status bits

There are ﬁve (5) status bits that are evaluated with each byte (or character) received:

received break, framing error, parity error, overrun error, and change of break. The ﬁrst

three are appended to each byte and stored in the RxFIFO.

The overrun error and change of break are not necessarily associated with the byte

presently being received. They are developed by the receiver state machine. They will

persist until a command to rest them is issued to the command register. A change of

break occurs on a beginning and the end of a break condition. The meaning of overrun is

that data has not been lost. All data before the overrun ﬂag is set if valid and available.

The receiver status bits are normally cleared by servicing the interrupt condition they

represent or by Rx reset or Rx disable commands or the several error reset commands in

the Command Register (CR).

The ‘received break’ will always be associated with a zero byte in the RxFIFO. It means

that zero character was a break character and not a zero data byte. The reception of a

break condition will always set the ‘change of break’ status bit in the Interrupt Status

The ‘change of break’ condition is reset by a reset error status command in the Command

A framing error occurs when a non-zero character was seen and that character has a zero

in the stop bit position.

The parity error indicates that the receiver-generated parity was not the same as that sent

by the transmitter.

The framing, parity and received break status bits are reset when the associated data byte

is read from the RxFIFO since these ‘error’ conditions are attached to the byte that has the

error.

The overrun error occurs when the RxFIFO is full, the receiver shift register is full, and

another start bit is detected. At this moment the receiver has 257 valid characters and the

start bit of the 258th has been seen. At this point the host has approximately 6

⁄

16-bit time to

read a byte from the RxFIFO or the overrun condition will be set. The 258th character then

overruns the 257th, and the 258th the 259th, and so on until an open position in the

RxFIFO is seen (‘seen’ meaning at least one byte was read from the RxFIFO).

Overrun is cleared by a use of the ‘error reset’ command in the Command Register.

The fundamental meaning of the overrun is that data has been lost. Data in the RxFIFO

remains valid. The receiver will begin placing characters in the RxFIFO as soon as a

position becomes vacant.

Remark: Precaution must be taken when reading an overrun FIFO. There will be 256

valid characters in the receiver FIFO. There will be one character in the receiver shift

received since the overrun bit was set. The 257th character received and read as valid but

it will not be known how many characters were lost between the two characters of the

256th and 257th reads of the RxFIFO. In the 8-bit mode, the numbers 8 and 9 replace the

numbers 256 and 257 above.

SC28L201 датащи(PDF) 22 Page - NXP Semiconductors

SC28L201 датащи(HTML) 22 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL