SC28L201 datasheet(11/110 Pages) NXP

11 / 110 page

9397 750 13138

Product data sheet

Rev. 01 — 31 October 2005

11 of 110

Philips Semiconductors

SC28L201

3.3 V, 5 V UART, 3.125 Mbit/s, with 256-byte FIFO

6.1.4 UART

The UART is a fully independent, full duplex and provides all normal asynchronous

functions: 5 to 8 data bits, parity odd or even, programmable stop bit length, false start bit

detection. Also provided are 256-byte FIFOs, Xon/Xoff software ﬂow control, RTS/CTS

hardware ﬂow control. The 9-bit mode address recognition with automatic RS485

turnaround. The BRG, Counter/Timer, or external clocks provide the baud rates. The

receivers and transmitters may operate in either the ‘1

×’ or ‘16×’ modes.

The control section recognizes two address schemes. One is the subset of the other: a

four (4) bit and a seven (7) bit address spaces. The purpose of this is to provide a large

degree of software compatibility with previous Philips/Signetics UARTs.

6.1.5 Transmitter and receiver

The transmitter and receiver are independent devices capable of full duplex operation.

Baud rates, interrupt and status conditions are under separate control. Transmitter has

automatic simplex ‘turnaround’. Receiver has RTS and Xon/Xoff ﬂow control and a

three-character recognition system.

6.1.6 Transmitter real time error check

This is a circuit used to verify that the correct data arrived at the destination. It is done real

time with one or two bit times of programmable delay. The purpose of this circuit is to

improve the response time of detecting problem data channels and to relieve the

processor burden and delay of checking data returned for validation.

The function is that the receiver returns the data received back to the transmitting station

where it is compared to a delayed version of the data sent. If an error occurs, and interrupt

may be generated for the particular bit that is in error. This is essentially a loopback

condition where circuits internal to the UART delay and compare the data returned.

It is suggested that a very high priority be set in the interrupt arbitration bidding control

6.1.7 FIFO structures

The FIFO structure is 256 bytes for each of the two FIFOs in the UART. They are

organized as 11-bit words for the receiver and 8-byte words for the transmitter. The

interrupt level may be set at any value from 0 to 255. The interrupt level is independently

set for each FIFO.

FIFO interrupt and DMA ﬁll/empty levels are controlled by the RXFIL and TXFIL registers

which may set any level of the from 0 to 255. The signals associated with the FIFO ﬁll

levels are available to the I/O pins (for interrupt or DMA) and to the arbitrating interrupt

system for ﬁne tuning of the arbitration authority.

6.1.8 Intelligent interrupt arbitration

The interrupt system uses a highly programmable arbitrating technique to establish when

an interrupt should be presented to the processor. The advantageous feature of this

system is the presentation of the context of the interrupt. It is presented in both a current

interrupt register and in the interrupt vector. The context of the interrupt shows the

interrupting channel, identiﬁes which of the 11 possible sources in requesting interrupt

service and in the case of a receiver or transmitter gives the current ﬁll level of the FIFO.

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