SC28L201 datasheet(6/110 Pages) NXP

6 / 110 page

9397 750 13138

Product data sheet

Rev. 01 — 31 October 2005

6 of 110

Philips Semiconductors

SC28L201

3.3 V, 5 V UART, 3.125 Mbit/s, with 256-byte FIFO

Pinning information

5.1 Pinning

5.2 Pin description

Fig 3.

Pin conﬁguration for TSSOP48; 80xxx mode

Fig 4.

Pin conﬁguration for TSSOP48; 68000 mode

SC28L201A1DGG

80xxx mode

VDD

X1/SCLK

IRQN

TXD

I/O0A

RXD

I/O1A

RESET

I/O2A

I/O3A

I/O4A

I/O5A

I/O6A

I/O7A

VSS

VDD

I/O0B

I/O2B

I/O3B

MODE_IM

I/O4B

I/O6B

RDN

WRN

IACKN

CEN

VSS

002aab421

VSS

VDD

VSS

VDD

VSS

SC28L201A1DGG

68xxx mode

VDD

X1/SCLK

IRQN

TXD

I/O0A

RXD

I/O1A

RESETN

I/O2A

I/O3A

I/O4A

I/O5A

I/O6A

I/O7A

VSS

VDD

I/O0B

I/O2B

I/O3B

MODE_IM

I/O4B

I/O6B

DACKN

R/WN

IACKN

CEN

VSS

002aab422

VSS

VDD

VSS

VDD

VSS

Table 2:

Pin description for 80xxx bus interface (Intel)

See Figure 3.

Symbol

Type

Description

MODE_IM

Bus conﬁguration. When HIGH or not connected conﬁgures the bus interface to

the conditions shown in this table.

D0 to D7

18, 17, 16,

15, 12, 11,

10, 9

I/O

Data bus. Bidirectional 3-state data bus used to transfer commands, data and status

between the UART and the CPU. D0 is the least signiﬁcant bit.

CEN

Chip Enable. Active LOW input signal. When LOW, data transfers between the CPU

and the UART are enabled on D[0:7] as controlled by the WRN, RDN and A6 to A0

inputs. When HIGH, places the D[0:7] lines in the 3-state condition.

WRN

Write strobe. When LOW and CEN is also LOW, the contents of the data bus is

loaded into the addressed register. The transfer occurs on the rising edge of the

signal.

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