SC28L201 datasheet(96/110 Pages) NXP

96 / 110 page

9397 750 13138

Product data sheet

Rev. 01 — 31 October 2005

96 of 110

Philips Semiconductors

SC28L201

3.3 V, 5 V UART, 3.125 Mbit/s, with 256-byte FIFO

12.1 Timing diagrams

The active time of read or write cycle exists only when CEN is LOW and RDN or CEN is

also LOW.

Write = CEN and WRN LOW.

Read = CEN and RDN LOW.

For the 68000 mode:

Write = CEN LOW and R/WN LOW and DACKN HIGH.

Read = CEN LOW and R/WN HIGH.

In general, it is convenient (but is not at all required) to think of the Read/Write signal to be

active and then let the CEN be the ‘strobing’ or clocking control. However, some users

have wired CEN LOW and allowed RDN or WRN to be the clocking or strobing input.

While this is completely within the speciﬁed limits, it is not recommended since it will

greatly increase the part’s sensitivity to noise ‘glitches’ on the RDN and WRN signals.

For the 68000 mode, the CEN is very much the clock or ‘strobing’ signal. The RDN and

WRN signals have been combined into the R/WN signal. Therefore, the part is always

prepared to do a write or read; it only needs CEN to enable.

In the 68000 mode design, care should be given to system drift over temperature, voltage,

and age when R/WN and CEN change very close to each other. If R/WN switches shortly

before CEN (due to system drift) it is possible to produce very short internal read or write

pulses which could change internal controls, FIFO address pointers, for example.

Figure 5 loosely shows the timing conditions that may exist of the active area those

signals will produce.

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