SC28L201 datasheet(10/110 Pages) NXP

10 / 110 page

9397 750 13138

Product data sheet

Rev. 01 — 31 October 2005

10 of 110

Philips Semiconductors

SC28L201

3.3 V, 5 V UART, 3.125 Mbit/s, with 256-byte FIFO

6.1.2 Timing circuits

6.1.2.1

Crystal oscillator

The crystal oscillator is the main timing element for the SC28L201. It is nominally set at

14.7456 MHz. Operation with a crystal as a frequency standard is speciﬁed from 7 MHz to

16.2 MHz. The use of an external clock allows all frequencies to 50 MHz. Clock prescalers

are provided to match various available system clocks to those needed for baud rate

generation.

Remark: If an external clock is used, X2 should not drive more than 2 CMOS or 2 TTL

equivalents.

6.1.2.2

Fixed rate Baud Rate Generator (BRG)

The BRG is driven by the X1/SCLK input through a programmable prescale divider. It

generates all of the 27 ‘ﬁxed’ internal baud rates. This baud rate generator is designed to

generate the industry standard baud rates from a 14.7456 MHz crystal or clock frequency.

X1/SCLK frequencies different from 14.7456 MHz will cause the ‘ﬁxed’ baud rates to

change by exactly the ratio of 14.7456 to the different frequency.

6.1.2.3

Counter/Timer

The two Counter/Timers are programmable 16-bit ‘down’ counters. It provides

miscellaneous baud rates, timing periods and acts as an extra watchdog timer for the

receivers. It has 8 programmable clock sources derived from internal and external signals.

It may also act as a character counter for the receiver. Interrupts from the Counter/Timer

are generated as it passes through zero.

6.1.2.4

Programmable BRG (PBRG)

This is another 16-bit programmable counter to generate only baud rates or

miscellaneous clock frequencies. Its output is available to the receiver and transmitter and

may be delivered to I/O ports. It has 8 programmable clock sources derived from internal

and external signals.

6.1.3 I/O ports

The SC28L201 is provided with 14 I/O ports. These ports are true input and/or output

structures and are equipped with a change of state detector. The input circuit of these pins

is always active. Under program control the ports my display internal signals or static logic

levels. The functions represented by the I/O ports include hardware ﬂow control. Modem

signals, signals for interrupt conditions or various internal clocks and timing intervals.

Each I/O pin has a change of state detector attached to it. These are used to alert the

processor to slow or infrequent signals, modem signals, alarm, power alerts, and so on.

For the signals to qualify for Change-Of-State (COS) detection, the signal must be stable

for a time of 25

µs to 50 µs (one to two cycles of the 38.4 kBd clock).

The input logic of these pins is always active, even when deﬁned as an output. Therefore,

it would be possible for the chip to count the number of times the RTS or CTS signal

occurred, thus giving an indication of interrupt latency.

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