SC28L201 datasheet(59/110 Pages) NXP

59 / 110 page

9397 750 13138

Product data sheet

Rev. 01 — 31 October 2005

59 of 110

Philips Semiconductors

SC28L201

3.3 V, 5 V UART, 3.125 Mbit/s, with 256-byte FIFO

8.2.10 Receiver FIFO (RxFIFO)

The FIFO for the receiver is 11 bits wide and 256 words deep. The status of each byte

received is stored with that byte and is moved along with the byte as the characters are

read from the FIFO. The upper three bits are presented in the Status Register and they

change in the Status Register each time a data byte is read from the FIFO. Therefore, the

Status Register should be read before the byte is read from the RxFIFO if one wishes to

ascertain the quality of the byte.

The foregoing applies to the ‘character error mode’ of status reporting. See MR1[5] in

Table 17 and RxFIFO descriptions for ‘block error’ status reporting. Brieﬂy, Block Error

gives the accumulated error of all bytes received by the RxFIFO since the last Reset Error

command was issued (CR = 0x04).

[1]

These bits are sent to the Status Register.

8.2.11 Transmitter FIFO (TxFIFO)

The FIFO for the transmitter is 8 bits wide by 256 bytes deep. For character lengths less

than 8 bits, the upper bits will be ignored by the transmitter state machine and thus are

effectively discarded.

8.2.12 Receiver FIFO Interrupt Level (RxFIL)

The position in the RxFIFO that causes the receiver will enter the interrupt arbitration

process. This register is used to offset the effect of the arbitration threshold. It use may

yield moderate improvements in the interrupt service. It will also ‘equalize’ interrupt

latency and allow for larger aggregate block transfers between fast and slow channels.

Writing to this register removes the interrupt control established in MR0 and MR1.

Table 27:

RxFIFO - Receiver FIFO register (address 0x03) bit description

Bit

Symbol

Description

10 [1]

break received status

9 [1]

framing error status

8 [1]

parity error status

7:0

This is the data byte sent to the data bus on RxFIFO read.

8 data bits. MSBs = 0 for 7, 6, 5 bit data.

Table 28:

TxFIFO - Transmitter FIFO register (address 0x03) bit description

Bit

Symbol

Description

7:0

8 data bits. MSBs are ignored to 0 for 7, 6, 5 bit data.

Table 29:

RxFIL - Receiver FIFO Interrupt Level register (address 0x46) bit description

Bit

Symbol

Description

7:0

any one of 256 FIFO ﬁll positions

SC28L201 датащи(PDF) 59 Page - NXP Semiconductors

SC28L201 датащи(HTML) 59 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL