SC28L201 datasheet(67/110 Pages) NXP

67 / 110 page

9397 750 13138

Product data sheet

Rev. 01 — 31 October 2005

67 of 110

Philips Semiconductors

SC28L201

3.3 V, 5 V UART, 3.125 Mbit/s, with 256-byte FIFO

8.4.7 Counter/Timer Preset Upper and Counter/Timer Preset Lower (CTPU, CTPL)

The CTPU and CTPL hold the eight MSBs and eight LSBs, respectively, of the value to be

used by the Counter/Timer in either the counter or timer modes of operation. The

minimum value that may be loaded into the CTPU/CTPL registers is 0x0000. Note that

these registers are write-only and cannot be read by the CPU.

In the timer mode, the C/T generates a square wave whose period is twice the value (in

C/T clock periods) of the CTPU and CTPL. The waveform so generated is often used for a

data clock. The formula for calculating the divisor ‘n’ to load to the CTPU and CTPL for a

particular 1

× data clock is shown in Equation 2.

(2)

Remark: The 2 in the denominator is for the square wave generation. For the Pulse mode,

change the 2 to a 1. This doubles the C/T output speeds for any given input clock.

Often this division will result in a non-integer value: 26.3 for example. One may only

program integer numbers to a digital divider. Therefore, 26 (0x001A) would be chosen. If

26.7 were the result of the division, then 27 (0x0017) would be chosen. This gives a baud

rate error of 0.3/26.3 or 0.3/26.7 that yields a percentage error of 1.14 % or 1.12 %,

respectively, well within the ability of the asynchronous mode of operation. Higher input

frequency to the counter reduces the error effect of the fractional division.

PBRG 0 register control

0 = resets PBRG 0 and holds it stopped

1 = allows PBRG 0 to run

2:0

PBRG 0 clock selection

000 = SCLK

001 = SCLK/2

010 = SCLK/16

011 = SCLK/32

100 = SCLK/64

101 = SCLK/128

110 = I/O3A

111 = reserved

Table 43:

PBRGCS - Programmable BRG Clock Source 0 and 1 register (address 0x33) bit

description …continued

Bit

Symbol

Description

Table 44:

CTPU - Counter/Timer Preset Upper 0 and 1 register (address 0x16, 0x1E)

bit description

Bit

Symbol

Description

7:0

The lower eight (8) bits for the 16-bit Counter/Timer Preset register

Table 45:

CTPL - Counter/Timer Preset Lower 0 and 1 register (address 0x17, 0x1F)

bit description

Bit

Symbol

Description

7:0

The upper eight (8) bits for the 16-bit Counter/Timer Preset register

C/T clock input frequency

216

baud rate desired

()

------------------------------------------------------------------------

SC28L201 датащи(PDF) 67 Page - NXP Semiconductors

SC28L201 датащи(HTML) 67 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL