ATtiny167-ESSZ datasheet(158/282 Pages) ATMEL

158 / 282 page

158

7728D–AVR–07/09

ATtiny87/ATtiny167

• Bits 3:0 – USICNT3..0: Counter Value

These bits reflect the current 4-bit counter value. The 4-bit counter value can directly be read

or written by the CPU.

The 4-bit counter increments by one for each clock generated either by the external clock

edge detector, by a Timer/Counter0 Compare Match, or by software using USICLK or USITC

strobe bits. The clock source depends of the setting of the USICS1..0 bits. For external clock

operation a special feature is added that allows the clock to be generated by writing to the

USITC strobe bit. This feature is enabled by write a one to the USICLK bit while setting an

external clock source (USICS1 = 1).

Note that even when no wire mode is selected (USIWM1..0 = 0) the external clock input

(USCK/SCL) are can still be used by the counter.

14.5.4

USICR – USI Control Register

The Control Register includes interrupt enable control, wire mode setting, Clock Select setting,

and clock strobe.

• Bit 7 – USISIE: Start Condition Interrupt Enable

Setting this bit to one enables the Start Condition detector interrupt. If there is a pending inter-

rupt when the USISIE and the Global Interrupt Enable Flag is set to one, this will immediately

be executed. Refer to the USISIF bit description on page 157 for further details.

• Bit 6 – USIOIE: Counter Overflow Interrupt Enable

Setting this bit to one enables the Counter Overflow interrupt. If there is a pending interrupt

when the USIOIE and the Global Interrupt Enable Flag is set to one, this will immediately be

executed. Refer to the USIOIF bit description on page 157 for further details.

• Bit 5:4 – USIWM1:0: Wire Mode

These bits set the type of wire mode to be used. Basically only the function of the outputs are

affected by these bits. Data and clock inputs are not affected by the mode selected and will

always have the same function. The counter and USI Data Register can therefore be clocked

externally, and data input sampled, even when outputs are disabled. The relations between

USIWM1:0 and the USI operation is summarized in Table 14-1.

Bit

USISIE

USIOIE

USIWM1

USIWM0

USICS1

USICS0

USICLK

USITC

USICR

Read/Write

R/W

Initial Value

ATtiny167-ESSZ датащи(PDF) 158 Page - ATMEL Corporation

ATtiny167-ESSZ датащи(HTML) 158 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL