ATtiny167-ESSZ datasheet(57/282 Pages) ATMEL

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7728D–AVR–07/09

ATtiny87/ATtiny167

6.3.3

Watchdog Timer Control Register - WDTCR

• Bit 7 - WDIF: Watchdog Interrupt Flag

This bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Timer is con-

figured for interrupt. WDIF is cleared by hardware when executing the corresponding interrupt

handling vector. Alternatively, WDIF is cleared by writing a logic one to the flag. When the I-bit

in SREG and WDIE are set, the Watchdog Time-out Interrupt is executed.

• Bit 6 - WDIE: Watchdog Interrupt Enable

When this bit is written to one and the I-bit in the Status Register is set, the Watchdog Interrupt

is enabled. If WDE is cleared in combination with this setting, the Watchdog Timer is in Inter-

rupt Mode, and the corresponding interrupt is executed if time-out in the Watchdog Timer

occurs.

If WDE is set, the Watchdog Timer is in Interrupt and System Reset Mode. The first time-out in

the Watchdog Timer will set WDIF. Executing the corresponding interrupt vector will clear

WDIE and WDIF automatically by hardware (the Watchdog goes to System Reset Mode). This

is useful for keeping the Watchdog Timer security while using the interrupt. To stay in Interrupt

and System Reset Mode, WDIE must be set after each interrupt. This should however not be

done within the interrupt service routine itself, as this might compromise the safety-function of

the Watchdog System Reset mode. If the interrupt is not executed before the next time-out, a

System Reset will be applied.

If the Watchdog Timer is used as clock monitor (c.f. Section • “Bits 3:0 – CLKC3:0: Clock Con-

trol Bits 3 - 0” on page 40), the System Reset Mode is enabled and the Interrupt Mode is

automatically disabled.

Note:

1. At least one of these three enables (WDTON, WDE & WDIE) equal to 1.

• Bit 4 - WDCE: Watchdog Change Enable

This bit is used in timed sequences for changing WDE and prescaler bits. To clear the WDE

bit, and/or change the prescaler bits, WDCE must be set.

Once written to one, hardware will clear WDCE after four clock cycles.

Bit

543210

WDIF

WDIE

WDP3

WDCE

WDE

WDP2

WDP1

WDP0

WDTCR

Read/Write

R/W

Initial Value

Table 6-1.

Watchdog Timer Configuration

Clock

Monitor

WDTON

WDE

WDIE Mode

Action on Time-out

Stopped

None

y(1)

System Reset Mode

Reset

Off

Interrupt Mode

Interrupt

System Reset Mode

Reset

Interrupt and System Reset

Mode

Interrupt, then go to System

Reset Mode

System Reset Mode

Reset

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